參數(shù)資料
型號(hào): MCP6S28
廠商: Microchip Technology Inc.
元件分類(lèi): FPGA
英文描述: 400000 SYSTEM GATE 2.5 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述: 單端,軌至軌I / O,低增益美國(guó)PGA
文件頁(yè)數(shù): 2/43頁(yè)
文件大?。?/td> 880K
代理商: MCP6S28
MCP6S21/2/6/8
DS21117A-page 2
2003 Microchip Technology Inc.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings
V
DD
- V
SS
.........................................................................7.0V
All inputs and outputs.......................V
SS
- 0.3V to V
DD
+0.3V
Difference Input voltage ........................................|V
DD
- V
SS
|
Output Short Circuit Current...................................continuous
Current at Input Pin
.............................................................±
2 mA
Current at Output and Supply Pins
................................±
30 mA
Storage temperature .....................................-65°C to +150°C
Junction temperature ..................................................+150°C
ESD protection on all pins (HBM;MM)
.................. ≥
2 kV; 200V
Notice:
Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
device reliability.
DC CHARACTERISTICS
PIN FUNCTION TABLE
Name
Function
V
OUT
CH0-CH7
V
SS
V
DD
SCK
SI
SO
CS
V
REF
Analog Output
Analog Inputs
Negative Power Supply
Positive Power Supply
SPI Clock Input
SPI Serial Data Input
SPI Serial Data Output
SPI Chip Select
External Reference Pin
Electrical Specifications:
Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R
L
= 10 k
to V
DD
/2, SI and SCK are tied low and CS is tied high.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Amplifier Input
Input Offset Voltage
Input Offset Voltage Drift
Power Supply Rejection Ratio
Input Bias Current
Input Bias Current over
Temperature
Input Impedance
Input Voltage Range
Amplifier Gain
Nominal Gains
DC Gain Error
V
OS
-275
70
±4
85
±1
+275
250
μV
G = +1, V
DD
= 4.0V
T
A
= -40 to +85°C
G = +1
(Note 1)
CHx = V
DD
/2
T
A
= -40 to +85°C,
CHx = V
DD
/2
V
OS
/
T
A
PSRR
I
B
I
B
μV/°C
dB
pA
pA
Z
IN
V
IVR
10
13
||15
||pF
V
V
SS
0.3
V
DD
+0.3
G
g
E
g
E
-0.1
-1.0
3.4
1 to 32
±0.0002
±0.0004
4.9
+0.028
+0.1
+1.0
6.4
V/V
%
%
%/°C
%/°C
k
%/°C
+1, +2, +4, +5, +8, +10, +16 or +32
V
OUT
0.3V to V
DD
0.3V
V
OUT
0.3V to V
DD
0.3V
T
A
= -40 to +85°C
T
A
= -40 to +85°C
(Note 1)
(Note 1)
T
A
= -40 to +85°C
G = +1
G
+2
G = +1
G
+2
DC Gain Drift
G/
T
A
G/
T
A
R
LAD
R
LAD
/
T
A
Internal Resistance
Internal Resistance over
Temperature
Amplifier Output
DC Output Non-linearity G = +1
V
ONL
V
ONL
V
OH
, V
OL
±0.003
±0.001
% of FSR V
OUT
= 0.3V to V
DD
0.3V, V
DD
= 5.0V
% of FSR V
OUT
= 0.3V to V
DD
0.3V, V
DD
= 5.0V
mV
G
+2; 0.5V output overdrive
G
+2; 0.5V output overdrive,
V
REF
= V
DD
/2
mA
G
+2
Maximum Output Voltage Swing
V
SS
+20
V
SS
+60
V
DD
-100
V
DD
-60
Short-Circuit Current
Note
1:
I
O(SC)
±30
R
LAD
(R
F
+ R
G
in Figure 4-1) connects V
REF
, V
OUT
and the inverting input of the internal amplifier. The MCP6S22 has
V
REF
tied internally to V
SS
, so V
SS
is coupled to the internal amplifier and the PSRR spec describes PSRR+ only. We
recommend the MCP6S22’s V
SS
pin be tied directly to ground to avoid noise problems.
I
Q
includes current in R
LAD
(typically 60 μA at V
OUT
= 0.3V). Both I
Q
and I
Q_SHDN
exclude digital switching currents.
The output goes Hi-Z and the registers reset to their defaults; see Section 5.4, “Power-On Reset”.
2:
3:
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