fSCL
參數(shù)資料
型號: MCP3427-E/MF
廠商: Microchip Technology
文件頁數(shù): 20/56頁
文件大小: 0K
描述: IC ADC 16BIT I2C PROGBL 10-DFN
產(chǎn)品培訓(xùn)模塊: MCP3901 Analog Front End
標(biāo)準(zhǔn)包裝: 120
位數(shù): 16
采樣率(每秒): 15
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 10-VFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 10-DFN-EP(3x3)
包裝: 管件
輸入數(shù)目和類型: 2 個差分,單極
產(chǎn)品目錄頁面: 672 (CN2011-ZH PDF)
2009 Microchip Technology Inc.
DS22226A-page 27
MCP3426/7/8
High Speed Mode (3.4 MHz)
Clock frequency
fSCL
0—
3.4
MHz
Cb = 100 pF
0—
1.7
MHz
Cb = 400 pF
Clock high time
THIGH
60
ns
Cb = 100 pF, fSCL = 3.4 MHz
120
ns
Cb = 400 pF, fSCL = 1.7 MHz
Clock low time
TLOW
160
ns
Cb = 100 pF, fSCL = 3.4 MHz
320
ns
Cb = 400 pF, fSCL = 1.7 MHz
SCL rise time
TR
40
ns
From VIL to VIH,
Cb = 100 pF, fSCL = 3.4 MHz
80
ns
From VIL to VIH,
Cb = 400 pF, fSCL = 1.7 MHz
SCL fall time
TF
40
ns
From VIH to VIL,
Cb = 100 pF, fSCL = 3.4 MHz
80
ns
From VIH to VIL,
Cb = 400 pF, fSCL = 1.7 MHz
SDA rise time
TR: DAT
80
ns
From VIL to VIH,
Cb = 100 pF, fSCL = 3.4 MHz
160
ns
From VIL to VIH,
Cb = 400 pF, fSCL = 1.7 MHz
SDA fall time
TF: DATA
80
ns
From VIH to VIL,
Cb = 100 pF, fSCL = 3.4 MHz
160
ns
From VIH to VIL,
Cb = 400 pF, fSCL = 1.7 MHz
Data hold time
THD:DAT
0
70
ns
Cb = 100 pF, fSCL = 3.4 MHz
0
150
ns
Cb = 400 pF, fSCL = 1.7 MHz
Output valid from clock
(Notes 2 and 3)
TAA
150
ns
Cb = 100 pF, fSCL = 3.4 MHz
310
ns
Cb = 400 pF, fSCL = 1.7 MHz
START condition hold time
THD:STA
160
ns
After this period, the first clock
pulse is generated
Repeated START condition
setup time
TSU:STA
160
ns
Only relevant for repeated Start
condition
Data input setup time
TSU:DAT
10
ns
STOP condition setup time
TSU:STO
160
ns
Input filter spike suppression
TSP
0
10
ns
SDA and SCL pins (Note 5)
TABLE 5-5:
I2C SERIAL TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V to +5.0V,
VSS = 0V, CHn+ = CHn- = VREF/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note
1:
This parameter is ensured by characterization and not 100% tested.
2:
This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3:
If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this
parameter is too long, Clock Low time (TLOW) can be affected.
4:
For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or
Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
5:
This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.
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