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參數(shù)資料
| 型號： | MCP3421A5T-E/OT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 27/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 3.75SPS SOT23-6 |
| 標準包裝： | 1 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 3.75 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-6 |
| 供應商設(shè)備封裝： | SOT-23-6 |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 2 個單端，雙極；1 個差分，單極 |
| 配用： | MCP3421EV-ND - BOARD EVAL FOR MCP3421 SOT23-6 |
| 其它名稱： | MCP3421A5T-E/OTDKR |
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MCP3421
DS22003B-page 6
2006 Microchip Technology Inc.
3.0
PIN DESCRIPTIONS
TABLE 3-1:
PIN FUNCTION TABLE
3.1
Analog Inputs (VIN+, VIN-)
VIN+ and VIN- are differential signal input pins. The
MCP3421 device accepts a fully differential analog
input signal which is connected on the VIN+ and VIN-
input pins. The differential voltage that is converted is
defined by VIN = (VIN+ - VIN-) where VIN+ is the voltage
applied at the VIN+ pin and VIN- is the voltage applied
at the VIN- pin. The input signal level is amplified by the
programmable gain amplifier (PGA) before the
conversion. The differential input voltage should not
exceed an absolute of (2* VREF/PGA) for accurate
measurement, where VREF is the internal reference
voltage (2.048V) and PGA is the PGA gain setting. The
converter output code will saturate if the input range
exceeds (2* VREF/PGA).
The absolute voltage range on each of the differential
input pins is from VSS-0.3V to VDD+0.3V. Any voltage
above or below this range will cause leakage currents
through the Electrostatic Discharge (ESD) diodes at
the input pins. This ESD current can cause unexpected
performance of the device. The common mode of the
analog inputs should be chosen such that both the
differential analog input range and the absolute voltage
range on each pin are within the specified operating
range
defined
in
3.2
Supply Voltage (VDD, VSS)
VDD is the power supply pin for the device. This pin
requires an appropriate bypass capacitor of about
0.1 F (ceramic) to ground. An additional 10 F
capacitor (tantalum) in parallel is also recommended
to further attenuate high frequency noise present in
some application boards. The supply voltage (VDD)
must be maintained in the 2.7V to 5.5V range for spec-
ified operation.
VSS is the ground pin and the current return path of the
device. The user must connect the VSS pin to a ground
plane through a low impedance connection. If an
analog ground path is available in the application PCB
(printed circuit board), it is highly recommended that
the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board.
3.3
Serial Clock Pin (SCL)
SCL is the serial clock pin of the I2C interface. The
MCP3421 acts only as a slave and the SCL pin
accepts only external serial clocks. The input data
from the Master device is shifted into the SDA pin on
the rising edges of the SCL clock and output from the
MCP3421 occurs at the falling edges of the SCL clock.
The SCL pin is an open-drain N-channel driver.
Therefore, it needs a pull-up resistor from the VDD line
to the SCL pin. Refer to Section 5.3 “I2C Serial Com-
communication.
3.4
Serial Data Pin (SDA)
SDA is the serial data pin of the I2C interface. The SDA
pin is used for input and output data. In read mode, the
conversion result is read from the SDA pin (output). In
write mode, the device configuration bits are written
(input) though the SDA pin. The SDA pin is an open-
drain N-channel driver. Therefore, it needs a pull-up
resistor from the VDD line to the SDA pin. Except for
start and stop conditions, the data on the SDA pin must
be stable during the high period of the clock. The high
or low state of the SDA pin can only change when the
clock signal on the SCL pin is low. Refer to Section 5.3
Serial Interface communication.
Pin No
Sym
Function
1VIN+
Non-Inverting Analog Input Pin
2VSS
Ground Pin
3SCL
Serial Clock Input Pin of the I2C Interface
4SDA
Bidirectional Serial Data Pin of the I2C Interface
5VDD
Positive Supply Voltage Pin
6VIN-
Inverting Analog Input Pin
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