參數(shù)資料
型號: MCP3421A5T-E/OT
廠商: Microchip Technology
文件頁數(shù): 23/30頁
文件大?。?/td> 0K
描述: IC ADC 18BIT 3.75SPS SOT23-6
標(biāo)準(zhǔn)包裝: 1
位數(shù): 18
采樣率(每秒): 3.75
數(shù)據(jù)接口: I²C,串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-6
供應(yīng)商設(shè)備封裝: SOT-23-6
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 2 個單端,雙極;1 個差分,單極
配用: MCP3421EV-ND - BOARD EVAL FOR MCP3421 SOT23-6
其它名稱: MCP3421A5T-E/OTDKR
2006 Microchip Technology Inc.
DS22003B-page 3
MCP3421
Integral Nonlinearity (Note 4)
INL
10
35
ppm of
FSR
DR = 3.75 SPS
Internal Reference Voltage
VREF
2.048
V
Gain Error (Note 5)
0.05
0.35
%
PGA = 1, DR = 3.75 SPS
PGA Gain Error Match (Note 5)
0.1
%
Between any 2 PGA gains
Gain Error Drift (Note 5)
5
40
ppm/°C
PGA=1, DR=3.75 SPS
Offset Error
VOS
15
40
V
Tested at PGA = 1
VDD = 5.0V and DR = 3.75 SPS
Offset Drift vs. Temperature
50
nV/°C
VDD = 5.0V
Common-Mode Rejection
105
dB
at DC and PGA =1,
110
dB
at DC and PGA =8,
TA = +25°C
Gain vs. VDD
5
ppm/V
TA = +25°C, VDD = 2.7V to 5.5V,
PGA = 1
Power Supply Rejection at DC
100
dB
TA = +25°C, VDD = 2.7V to 5.5V,
PGA = 1
Power Requirements
Voltage Range
VDD
2.7
5.5
V
Supply Current during
Conversion
IDDA
155
190
A
VDD = 5.0V
145
A
VDD = 3.0V
Supply Current during Standby
Mode
IDDS
—0.1
0.5
A
I2C Digital Inputs and Digital Outputs
High level input voltage
VIH
0.7 VDD
—VDD
V
Low level input voltage
VIL
0.3V
DD
V
Low level output voltage
VOL
——
0.4
V
I
OL = 3 mA, V
DD = +5.0V
Hysteresis of Schmitt Trigger
for inputs (Note 7)
VHYST
0.05VDD
——
V
fSCL = 100 kHz
Supply Current when I2C bus
line is active
IDDB
——
10
A
Input Leakage Current
IILH
——
1
A
VIH = 5.5V
IILL
-1
A
VIL = GND
Pin Capacitance and I2C Bus Capacitance
Pin capacitance
CPIN
10
pF
I2C Bus Capacitance
Cb
400
pF
Thermal Characteristics
Specified Temperature Range
TA
-40
+85
°C
Operating Temperature Range
TA
-40
+125
°C
Storage Temperature Range
TA
-65
+150
°C
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,
VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full-scale range.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Note 1:
Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.
This parameter is ensured by characterization and not 100% tested.
2:
This input impedance is due to 3.2 pF internal input sampling capacitor.
3:
The total conversion speed includes auto-calibration of offset and gain.
4:
INL is the difference between the endpoints line and the measured code at the center of the quantization band.
5:
Includes all errors from on-board PGA and VREF.
6:
Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA.
7:
This parameter is ensured by characterization and not 100% tested.
8:
This parameter is ensured by design and not 100% tested.
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