參數(shù)資料
型號: MCM72FB8ML
廠商: Motorola, Inc.
元件分類: FPGA
英文描述: 600000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN
中文描述: 256 × 72比特突發(fā)內(nèi)存多芯片模塊
文件頁數(shù): 8/20頁
文件大?。?/td> 252K
代理商: MCM72FB8ML
MCM72FB8ML MCM72PB8ML
8
MOTOROLA FAST SRAM
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V
Vin
VDD)
Output Leakage Current (0 V
Vin
VDDQ)
AC Supply Current (Device Selected,
All Outputs Open, Freq = Max, VDD = Max, VDDQ = Max)
Includes Supply Current from Both VDD and VDDQ
Ilkg(I)
Ilkg(O)
IDDA
±
1
μ
A
±
1
μ
A
1700
mA
1, 2, 3
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels)
ISB2
TBD
mA
4. 5
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels)
ISB3
TBD
mA
4, 6
Clock Running (Device Deselected, Freq = Max,
VDD = Max, VDDQ = Max, All Inputs Toggling at
CMOS Levels)
ISB4
TBD
mA
4. 5
Static Clock Running (Device Deselected, Freq = Max,
VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels)
ISB5
TBD
mA
4, 6
Output Low Voltage (IOL = 2 mA) VDDQ = 2.5 V
Output High Voltage (IOH = – 2 mA) VDDQ = 2.5 V
Output Low Voltage (IOL = 8 mA) VDDQ = 3.3 V
Output High Voltage (IOH = – 4 mA) VDDQ = 3.3 V
NOTES:
1. Reference AC Operating Conditions and Characteristics for input and timing.
2. All addresses transition simultaneously low (LSB) then high (MSB).
3. Data states are all zero.
4. Device is deselected as defined by the Truth Table.
5. CMOS levels for I/O’s are VIT
VSS + 0.2 V or
VDDQ – 0.2 V. CMOS levels for other inputs are Vin
VSS + 0.2 V or
VDD – 0.2 V.
6. TTL levels for I/O’s are VIT
VIL or
VIH2. TTL levels for other inputs are Vin
VIL or
VIH.
VOL1
VOH1
VOL2
VOH2
0.7
V
1.7
V
0.4
V
2.4
V
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70
°
C
, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
CI/O
16
pF
Input/Output Capacitance
5
pF
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