- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371096 > MCM72FB8ML (Motorola, Inc.) 600000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN PDF資料下載
參數(shù)資料
| 型號： | MCM72FB8ML |
| 廠商： | Motorola, Inc. |
| 元件分類： | FPGA |
| 英文描述： | 600000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 256 × 72比特突發(fā)內(nèi)存多芯片模塊 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 252K |
| 代理商： | MCM72FB8ML |
MCM72FB8ML MCM72PB8ML
14
MOTOROLA FAST SRAM
APPLICATION INFORMATION
STOP CLOCK OPERATION
In the stop clock mode of operation, the SRAM will hold all
state and data values even though the clock is not running
(full static operation). The SRAM design allows the clock to
start with ADSP and ADSC, and stops the clock after the last
write data is latched, or the last read data is driven out.
When starting and stopping the clock, the AC clock timing
and parametrics must be strictly maintained. For example,
clock pulse width and edge rates must be guaranteed when
starting and stopping the clocks.
To achieve the lowest power operation for all three stop
clock modes, stop read, stop write, and stop deselect:
1. Force the clock to a low state.
2. Force the control signals to an inactive state (this guar-
antees any potential source of noise on the clock input
will not start an unplanned on activity).
3. Force the address inputs to a low state.
K
ADSP
ADDRESS
ADV
A1
A2
Q(A1 + 1)
Q(A2)
Q(A1)
ADSP
(INITIATES
BURST READ)
CLOCK STOP
(CONTINUE
BURST READ)
WAKE UP ADSP
(INITIATES BURST READ)
NOTE: For lowest possible power consumption during stop clock, the addresses should be driven to a low state (VIL).
Best results are obtained if VIL < 0.2 V.
DQx
MCM72PB8ML PIPELINE STOP CLOCK WITH READ TIMING
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCM72FB8ML8 | 600,000 SYSTEM GATE 1.8 VOLT FPGA - NOT RECOMMENDED for NEW DESIGN |
| MCR102 | Silicon Controlled Rectifiers |
| MCR103 | Silicon Controlled Rectifiers |
| MCR225FP | Silicon Controlled Rectifiers |
| MCR506 | Silicon Controlled Rectifiers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM72FB8ML7.5 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256K x 72 Bit Burst RAM Multichip Module |
| MCM72FB8ML7.5R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256K x 72 Bit Burst RAM Multichip Module |
| MCM72FB8ML8 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256K x 72 Bit Burst RAM Multichip Module |
| MCM72FB8ML8R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256K x 72 Bit Burst RAM Multichip Module |
| MCM72JG32 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:256KB and 512KB Pipelined BurstRAM Secondary Cache Module for Pentium |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。