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參數(shù)資料
| 型號： | MCM69R738C |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4M-bit Synchronous Late Write Fast SRAM(4M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 4分位同步后寫入快速靜態(tài)存儲器（4分位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 301K |
| 代理商： | MCM69R738C |
MCM69R738C
MCM69R820C
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
5%, 0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
Output Timing Reference Level
0 to 2.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
1 V/ns (20% to 80%)
. . . . . . . . . . . . . .
1.25 V
1.25 V
. . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Timing Reference Level
Clock Input Pulse Level
R
θ
JA Device
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Cross–Point
1.8 V to 2.1 V
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
22
°
C/W
READ/WRITE CYCLE TIMING
69R738C–4
69R820C–4
69R738C–4.4
69R820C–4.4
69R738C–5
69R820C–5
69R738C–6
69R820C–6
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQX1
tKHQV
tKHQX
tKHQZ
tGLQX
4
—
4.4
—
5
—
6
—
ns
Clock High Pulse Width
1.5
—
1.5
—
2
—
2.4
—
ns
Clock Low Pulse Width
1.5
—
1.5
—
2
—
2.4
—
ns
Clock High to Output Low–Z
0.5
—
1
—
1
—
1
—
ns
1, 2
Clock High to Output Valid
—
2
—
2.2
—
2.5
—
3
ns
Clock High to Output Hold
0.7
—
0.7
—
1
—
1
—
ns
1
Clock High to Output High–Z
—
2
—
2.2
—
2.5
—
3
ns
1, 2
Output Enable Low to Output
Low–Z
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable Low to Output
Valid
tGLQV
—
2
—
2.2
—
2.5
—
3
ns
Output Enable to Output Hold
tGHQX
tGHQZ
0.5
—
0.5
—
0.5
—
0.5
—
ns
Output Enable High to Output
High–Z
—
2
—
2
—
2.5
—
3
ns
1, 2
ZZ High to Sleep Mode
tZZE
tZZR
tAVKH
tDVKH
tSVKH
tWVKH
tKHAX
tKHDX
tKHSX
tKHWX
—
50
—
50
—
50
—
50
ns
ZZ Low to Recovery
200
—
200
—
200
—
200
—
ns
Setup Times:
Address
Data In
Chip Select
Write Enable
0.5
—
0.5
—
0.5
—
0.5
—
ns
Hold Times:
Address
Data In
Chip Select
Write Enable
0.75
—
0.75
—
1
—
1
—
ns
NOTES:
1. This parameter is sampled and not 100% tested.
2. Measured at
±
200 mV from steady state.
DEVICE
UNDER
TEST
50
50
VDDQ/2
TIMING LIMITS
The table of timing values shows either a mini-
mum or a maximum limit for each parameter. Input
requirements are specified from the external system
point of view. Thus, address setup time is shown as
a minimum since the system must supply at least
that much time. On the other hand, responses from
the memory are specified from the device point of
view. Thus, the access time is shown as a maximum
since the device never provides data later than that
time.
Figure 1. AC Test Load
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69R738CZP4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R738CZP4.4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R738CZP4.4R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R738CZP4R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R738CZP5 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
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