參數(shù)資料
型號: MCM69R738C
廠商: Motorola, Inc.
英文描述: 4M-bit Synchronous Late Write Fast SRAM(4M位同步遲寫、快速靜態(tài)RAM)
中文描述: 4分位同步后寫入快速靜態(tài)存儲器(4分位同步遲寫,快速靜態(tài)內(nèi)存)
文件頁數(shù): 19/20頁
文件大?。?/td> 301K
代理商: MCM69R738C
MCM69R738C
MCM69R820C
19
MOTOROLA FAST SRAM
STANDARD (PUBLIC) INSTRUCTION CODES
Instruction
Code*
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
DQ pins
to High–Z state.
NOT IEEE 1149.1 COMPLIANT.
IDCODE
001**
Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation. Does not implement IEEE 1149.1 PRELOAD function.
NOT IEEE 1149.1
COMPLIANT.
BYPASS
111
Places the bypass register between TDI and TDO. Does not affect RAM operation.
SAMPLE–Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
DQ pins
to High–Z state.
*Instruction codes expressed in binary; MSB on left, LSB on right.
**Default instruction automatically loaded at power up and in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
Code*
Description
NO OP
011
Do not use these instructions; they are reserved for future use.
NO OP
101
Do not use these instructions; they are reserved for future use.
NO OP
110
Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary, MSB on left, LSB on right.
CAPTURE–DR
EXIT1–DR
EXIT2–DR
UPDATE–DR
CAPTURE–IR
EXIT1–IR
EXIT2–IR
UPDATE–IR
SHIFT–IR
PAUSE–IR
PAUSE–DR
TEST–LOGIC
RESET
RUN–TEST/
IDLE
SELECT
DR–SCAN
SELECT
IR–SCAN
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
0
Figure 5. TAP Controller State Diagram
0
SHIFT–DR
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