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參數(shù)資料
| 型號： | MCM69R738C |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4M-bit Synchronous Late Write Fast SRAM(4M位同步遲寫、快速靜態(tài)RAM) |
| 中文描述： | 4分位同步后寫入快速靜態(tài)存儲器（4分位同步遲寫，快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 301K |
| 代理商： | MCM69R738C |
MCM69R738C
MCM69R820C
13
MOTOROLA FAST SRAM
FUNCTIONAL OPERATION
READ AND WRITE OPERATIONS
All control signals except G are registered on the rising
edge of the CK clock. These signals must meet the setup
and hold times shown in the AC Characteristics table. On the
rising edge of the following clock, read data is clocked into
the output register and available at the outputs at tKHQV.
During this same cycle a new read address can be applied to
the address pins.
A deselect cycle (dead cycle) must occur prior to a write
cycle. Read cycles may follow write cycles immediately.
G, SS, and SW control output drive. Chip deselect via a
high on SS at the rising edge of CK clock has its effect on the
output drivers after the next rising edge of CK. SW low
deselects the output drivers immediately (on the same
cycle). Output selecting via a low on SS and high on SW at a
rising CK clock has its effect on the output drivers after the
next rising edge of CK. Output drive is also controlled directly
by output enable G. G is an asynchronous input. No clock
edges are required to enable/disable the output using G.
Output data will be valid the latter of tGLQV and tKHQV.
Outputs will begin driving at tKHQX1. Outputs will hold pre-
vious data until tKHQX or tGHQX.
WRITE AND BYTE WRITE FUNCTIONS
Note that in the following discussion the term “byte” refers
to nine bits of the RAM I/O bus. In all cases, the timing
parameters described for synchronous write input (SW),
apply to each of the byte write enable inputs (SBa, SBb,
etc.).
Byte write enable inputs have no effect on read cycles.
This allows the system designer not interested in performing
byte writes to connect the byte enable inputs to active low
(VSS). Reads of all bytes proceed normally and write cycles
activated via a low on SW and the rising edge of CK, write
the entire RAM I/O width. This way the designer is spared
having to drive multiple write input buffer loads.
Byte writes are performed using the byte write enable
inputs in conjunction with the synchronous write input (SW).
It is important to note that writing any one byte will inhibit a
read of all bytes at the current address. The RAM can not
simultaneously read one byte and write another at the same
address. A write cycle initiated with none of the byte write
enable inputs active, is neither a read or a write. No write will
occur, but the outputs will be deselected as in a normal write
cycle.
LATE WRITE
The write address is sampled on the first rising edge of
clock, and write data is sampled on the following rising edge.
The late write feature is implemented with single stage
write buffering. Write buffering is transparent to the user. A
comparator monitors the address bus and, when necessary,
routes buffer contents to the outputs to ensure coherent
operation. This occurs in all cases, whether there is a byte
write or a full word is written.
POWER UP AND INITIALIZATION
The following supply voltage application sequence is rec-
ommended: VSS, VDD, then VDDQ. Please note, per the
Absolute Maximum Ratings table, VDDQ is not to exceed
VDD + 0.5 V, whatever the instantaneous value of VDD. Once
supplies have reached specification levels, a minimum dwell
of 1.0 ms with CK clock inputs cycling is required before
beginning normal operations.
SLEEP MODE
This device is equipped with an optional sleep or low
power mode. The sleep mode pin is asynchronous and
active high. During normal operation, the ZZ pin is pulled low.
When ZZ is pulled high, the chip will enter sleep mode where
the device will meet the lowest possible power conditions.
The Sleep Mode Timing diagram shows the following modes
of operation: Normal Operation, No Read/Write Allowed, and
Sleep Mode.
Normal Operation
All inputs must meet setup and hold times prior to sleep
and tZZR nanoseconds after recovering from sleep. Clock
(CK) must also meet cycle high and low times during these
periods. Two cycles prior to sleep, initiation of either a read or
write operation is not allowed.
No Read/Write Allowed
During the period of time just prior to sleep and during
recovery from sleep, the assertion of any write or read signal
is not allowed. If a write or read operation occurs during
these periods, the memory array may be corrupted. Validity
of data out from the RAM can not be guaranteed immediately
after ZZ is asserted (prior to being in sleep). During sleep
mode recovery, the output impedance must be given
additional time above and beyond tZZR in order to match
desired impedance (see explanation in
Output Impedance
Circuitry
paragraph).
Sleep Mode
The RAM automatically deselects itself. The RAM discon-
nects its internal clock buffer. The external clock may con-
tinue to run without impacting the RAMs sleep current (IZZ).
All outputs will remain in a High–Z state while in sleep mode.
All inputs are allowed to toggle. The RAM will not be
selected, and perform any reads or writes.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MCM69R738CZP4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R738CZP4.4 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R738CZP4.4R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R738CZP4R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
| MCM69R738CZP5 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:4M Late Write 2.5 V I/O |
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