
MCM69R738C
MCM69R820C
5
MOTOROLA FAST SRAM
ABSOLUTE MAXIMUM RATINGS
(Voltages Referenced to VSS, See Note)
Rating
Symbol
Value
Unit
Core Supply Voltage
VDD
VDDQ
Vin
Iin
Iout
TA
Tbias
Tstg
–0.5 to 4.6
V
Output Supply Voltage
–0.5 to VDD + 0.5
–0.5 to VDD + 0.5
±
50
V
Voltage On Any Pin
V
Input Current (per I/O)
mA
Output Current (per I/O)
±
70
mA
Operating Temperature
0 to 70
°
C
Temperature Under Bias
–10 to 85
°
C
Storage Temperature
–55 to 125
°
C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
PBGA PACKAGE THERMAL CHARACTERISTICS
Rating
Symbol
Max
Unit
Notes
Junction to Ambient (Still Air)
R
θ
JA
R
θ
JA
R
θ
JA
R
θ
JB
R
θ
JC
53
°
C/W
1, 2
Junction to Ambient (@200 ft/min)
Single–Layer Board
38
°
C/W
1, 2
Junction to Ambient (@200 ft/min)
Four–Layer Board
22
°
C/W
Junction to Board (Bottom)
14
°
C/W
3
Junction to Case (Top)
5
°
C/W
4
NOTES:
1. Junction temperature is a function of on–chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38–87.
3. Indicates the average thermal resistance between the die and the printed circuit board.
4. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC–883
Method 1012.1).
CLOCK TRUTH TABLE
K
ZZ
SS
SW
SBa
SBb
SBc
SBd
DQ (n)
DQ (n+1)
Mode
L – H
L
L
H
X
X
X
X
X
Dout 0–35
Din 0–8
Din 9–17
Din 18–26
Din 27–35
Din 0–35
High–Z
Read Cycle All Bytes
L – H
L
L
L
L
H
H
H
High–Z
Write Cycle 1st Byte
L – H
L
L
L
H
L
H
H
High–Z
Write Cycle 2nd Byte
L – H
L
L
L
H
H
L
H
High–Z
Write Cycle 3rd Byte
L – H
L
L
L
H
H
H
L
High–Z
Write Cycle 4th Byte
L – H
L
L
L
L
L
L
L
High–Z
Write Cycle All Bytes
L – H
L
L
L
H
H
H
H
High–Z
Abort Write Cycle
L – H
L
H
H
X
X
X
X
X
High–Z
Deselect Cycle
L – H
L
H
L
X
X
X
X
High–Z
High–Z
Deselect Cycle
X
H
X
X
X
X
X
X
High–Z
High–Z
Sleep Mode
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
This device contains circuitry that will ensure
the output devices are in High–Z at power up.