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參數(shù)資料
| 型號： | MCM64E918 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8M Bit synchronous late write fast static RAM(8M位同步遲寫快速靜態(tài)RAM) |
| 中文描述： | 晚8分位同步靜態(tài)隨機存儲器寫入速度（800萬位同步遲寫快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/24頁 |
| 文件大?。?/td> | 503K |
| 代理商： | MCM64E918 |
MCM64E918
MCM64E836
1
MOTOROLA FAST SRAM
Motorola, Inc. 1999
Product Preview
8MB Double Data Rate HSTL I/O
Fast SRAM
The MCM64E918/MCM64E836 are 8M–bit pipelined burst synchronous late
write fast static RAMs designed to provide very high data bandwidth in secondary
cache applications. The MCM64E918 (organized as 512K words by 18 bits wide)
and the MCM64E836 (organized as 256K words by 36 bits wide) are fabricated
in Motorola’s high performance silicon gate MOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK, all addresses and burst control inputs are
registered. An internal buffer and special logic enables the memory to accept
write data on the rising or rising and falling edges of the clock, a cycle following
address and control signals. Read data is driven on the rising or rising and falling
edges of the CK clock and is referenced to echo clock (CQ and CQ) outputs.
The MCM64E918/MCM64E836 have HSTL inputs and outputs. The adjust-
able input trip–point (Vref) and output power supply voltage (VDDQ) gives
the system designer greater flexibility in optimizing system performance.
The impedance of the output buffers is programmable, allowing the outputs to
match the impedance of the circuit traces, which reduces signal reflections.
Single 2.5 V
±
5% Power Supply
Single Data Rate (SDR) and Double Data Rate (DDR) Burst Read and
Write
Pin Selectable Linear or Interleaved Burst Order
Four Tick Burst with Automatic Wrap–Around
Differential Clock Inputs
Active High and Active Low Echo Clock Outputs
1.8 V Expanded HSTL — I/O (JEDEC Standard JESD8–6 Class I
Compatible)
1.8 V Expanded HSTL — Compatible Programmable Impedance Output
Drivers
Pipelined (Register to Register) Synchronous Operation
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Stop Clock Functionality Supported
Optional x18 or x36 Organization
MCM64E918/MCM64E836–3.0 = 3.0 ns Clock Cycle Time
MCM64E918/MCM64E836–3.3 = 3.3 ns Clock Cycle Time
MCM64E918/MCM64E836–4.0 = 4.0 ns Clock Cycle Time
MCM64E918/MCM64E836–4.4 = 4.4 ns Clock Cycle Time
MCM64E918/MCM64E836–5.0 = 5.0 ns Clock Cycle Time
9 x 17 (153) Bump, 50 mil (1.27 mm) Pitch, 14 mm x 22 mm Flipped Chip
Plastic Ball Grid Array (PBGA) or Flipped Chip Ceramic Ball Grid Array
(CBGA) Packages
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MC64E918/D
SEMICONDUCTOR TECHNICAL DATA
MCM64E918
MCM64E836
FC PACKAGE
FLIPPED CHIP PBGA
CASE 1107A–01
RS PACKAGE
FLIPPED CHIP CBGA
CASE 1107B–01
8/25/99
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