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參數(shù)資料
| 型號： | MCM63Z736 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 128K x 36 Bit Synchronous Fast Static RAM(128K x 36位同步快速靜態(tài)RAM) |
| 中文描述： | 128K的× 36位同步快速靜態(tài)存儲器（128K的× 36位同步快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 135K |
| 代理商： | MCM63Z736 |
MCM63Z736 MCM63Z818
12
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
5%, TA = 0
°
to 70
°
C Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . .
1.5 V
0 to 3 V
. . . . . . . . . . . . . . .
1 V/ns (20% to 80%)
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . .
R
θ
JA Under Test
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 6 Unless Otherwise Noted
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TBD
READ/WRITE CYCLE TIMING
(See Notes 1 and 2)
MCM63Z736–143
MCM63Z818–143
143 MHz
MCM63Z736–133
MCM63Z818–133
133 MHz
MCM63Z736–100
MCM63Z818–100
100 MHz
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQV
tGLQV
tKHQX1
tKHQX
tGLQX
tGHQZ
tKHQZ
tADKH
tLVKH
tDVKH
tWVKH
tEVKH
tCVKH
7.0
—
7.5
—
10
—
ns
Clock High Pulse Width
2.8
—
3
—
4
—
ns
3
Clock Low Pulse Width
2.8
—
3
—
4
—
ns
3
Clock Access Time
—
4.0
—
4.2
—
5
ns
Output Enable to Output Valid
—
4.0
—
4.2
—
5
ns
Clock High to Output Active
1.5
—
1.5
—
1.5
—
ns
4, 5
Output Hold Time
1.5
—
1.5
—
1.5
—
ns
4
Output Enable to Output Active
0
—
0
—
0
—
ns
4, 5
Output Disable to Q High–Z
—
3.5
—
3.5
—
3.5
ns
4, 5
Clock High to Q High–Z
1.5
3.5
1.5
3.5
1.5
3.5
ns
4, 5
Setup Times:
Address
ADV
Data In
Write
Chip Enable
Clock Enable
2
2
1.7
2
2
2
—
2
2
1.7
2
2
2
—
2.2
2.2
2
2.2
2.2
2.2
—
ns
Hold Times:
Address
ADV
Data In
Write
Chip Enable
Clock Enable
tKHAX
tKHLX
tKHDX
tKHWX
tKHEX
tKHCX
0.5
—
0.5
—
0.5
—
ns
NOTES:
1. Write is defined as any SBx and SW low. Chip Enable is defined as SE1 low, SE2 high, and SB3 low whenever ADV is low.
2. All read and write cycle timings are referenced from CK or G.
3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC test conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
4. This parameter is sampled and not 100% tested.
5. Measured at
±
200 mV from steady state.
OUTPUT
Z0 = 50
RL = 50
1.5 V
Figure 6. AC Test Load
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