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參數(shù)資料
| 型號(hào)： | MCM63Z818 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 256Kx18 Bit Synchronous Fast Static RAM(256Kx18位同步快速靜態(tài)RAM) |
| 中文描述： | 256Kx18位同步快速靜態(tài)存儲(chǔ)器（256Kx18位同步快速靜態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 135K |
| 代理商： | MCM63Z818 |
MCM63Z736 MCM63Z818
1
MOTOROLA FAST SRAM
Motorola, Inc. 2000
128K x 36 and 256K x 18 Bit
Pipelined ZBT
RAM
Synchronous Fast Static RAM
The ZBT RAM is a 4M–bit synchronous fast static RAM designed to provide
Zero Bus Turnaround
. The ZBT RAM allows 100% use of bus cycles during
back–to–back read/write and write/read cycles. The MCM63Z736 (organized
as 128K words by 36 bits) and the MCM63Z818 (organized as 256K words by
18 bits) are fabricated in Motorola’s high performance silicon gate CMOS
technology. This device integrates input registers, an output register, a 2–bit
address counter, and high speed SRAM onto a single monolithic circuit for
reduced parts count in communication applications. Synchronous design
allows precise cycle control with the use of an external clock (CK). CMOS
circuitry reduces the overall power consumption of the integrated functions for
greater reliability.
Addresses (SA), data inputs (DQ), and all control signals except output enable
(G) and linear burst order (LBO) are clock (CK) controlled through positive–
edge–triggered noninverting registers.
Write cycles are internally self–timed and are initiated by the rising edge of the
clock (CK) input. This feature eliminates complex off–chip write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, pipelined SRAM output data is temporarily stored by an edge–
triggered output register and then released to the output buffers at the next rising
edge of clock (CK).
3.3 V LVTTL and LVCMOS Compatible
MCM63Z736/MCM63Z818–143 = 4 ns Access/7 ns Cycle (143 MHz)
MCM63Z736/MCM63Z818–133 = 4.2 ns Access/7.5 ns Cycle (133 MHz)
MCM63Z736/MCM63Z818–100 = 5 ns Access/10 ns Cycle (100 MHz)
Selectable Burst Sequencing Order (Linear/Interleaved)
Internally Self–Timed Write Cycle
Two–Cycle Deselect
Byte Write Control
ADV Controlled Burst
100–Pin TQFP Package
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc. and Motorola, Inc.
Order this document
by MCM63Z736/D
SEMICONDUCTOR TECHNICAL DATA
MCM63Z736
MCM63Z818
TQ PACKAGE
TQFP
CASE 983A–01
REV 7
5/19/00
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM63Z818TQ100 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM |
| MCM63Z818TQ100R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM |
| MCM63Z818TQ133 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM |
| MCM63Z818TQ133R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Pipelined ZBT RAM Synchronous Fast Static RAM |
| MCM63Z819TQ11 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 36 and 256K x 18 Bit Flow-Through ZBT RAM Synchronous Fast Static RAM |
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