參數(shù)資料
型號: MCM63Z736
廠商: Motorola, Inc.
英文描述: 128K x 36 Bit Synchronous Fast Static RAM(128K x 36位同步快速靜態(tài)RAM)
中文描述: 128K的× 36位同步快速靜態(tài)存儲器(128K的× 36位同步快速靜態(tài)內(nèi)存)
文件頁數(shù): 11/20頁
文件大?。?/td> 135K
代理商: MCM63Z736
MCM63Z736 MCM63Z818
11
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
5%, TA = 0
°
to 70
°
C Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS
(Voltages Referenced to VSS = 0 V)
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage
VDD
VDDQ*
VIL
VIH
VIH2
3.135
3.3
3.465
V
I/O Supply Voltage
3.135
3.3
VDD
0.8
V
Input Low Voltage
–0.3
V
Input High Voltage
2
VDD + 0.3
VDDQ + 0.3
V
Input High Voltage I/O Pins
* VDD and VDDQ are shorted together on the device and must be supplied with identical voltage levels.
2
V
VIH
20% tKHKH (MIN)
VSS
VSS – 1.0 V
Figure 5. Undershoot Voltage
DC CHARACTERISTICS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V
Vin
VDD)
Output Leakage Current (0 V
Vin
VDDQ)
AC Supply Current (Device Selected,
All Outputs Open, Freq = Max) Includes MCM63Z736/818–133
Supply Current for Both VDD and VDDQ MCM63Z736/818–100
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at CMOS Levels)
Ilkg(I)
Ilkg(O)
IDDA
±
1
μ
A
1
±
1
μ
A
MCM63Z736/818–143
515
505
405
mA
2, 3, 4
ISB2
40
mA
5, 6
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, VDDQ = Max, All Inputs Static at TTL Levels)
ISB3
145
mA
5, 7
Clock Running (Device Deselected,
Freq = Max, VDD = Max, All Inputs
Toggling at CMOS Levels)
MCM63Z736/818–143
MCM63Z736/818–133
MCM63Z736/818–100
ISB4
380
365
305
mA
5, 7
Hold Supply Current (Device Selected, Freq = Max, VDD = Max,
VDDQ = Max, CKE
VDD – 0.2 V, All Inputs Static at
CMOS Levels)
IDD1
80
mA
6
Output Low Voltage (IOL = 8 mA)
Output High Voltage (IOH = –8 mA)
NOTES:
1. LBO has an internal pullup and will exhibit leakage currents of
±
5
μ
A.
2. Reference AC Operating Conditions and Characteristics for Input and Timing.
3. All addresses transition simultaneously low (LSB) then high (MSB).
4. Data states are all zero.
5. Device in deselected mode as defined by the Truth Table.
6. CMOS levels for I/Os are VIT
VSS + 0.2 V or
VDDQ – 0.2 V. CMOS levels for other inputs are Vin
VSS + 0.2 V or
VDD – 0.2 V.
7. TTL levels for I/O’s are VIT
VIL or
VIH2. TTL levels for other inputs are Vin
VIL or
VIH.
VOL
VOH
0.4
V
2.4
V
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 0
°
to 70
°
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
CI/O
4
5
pF
Input/Output Capacitance
7
8
pF
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