參數(shù)資料
型號: MCF5372
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Microprocessor Data Sheet
中文描述: 微處理器數(shù)據(jù)表
文件頁數(shù): 21/42頁
文件大?。?/td> 787K
代理商: MCF5372
Preliminary Electrical Characteristics
MCF5373 ColdFire
Microprocessor Data Sheet, Rev. 0.3
Preliminary
Freescale Semiconductor
21
5.6
Oscillator and PLL Electrical Characteristics
5.7
External Interface Timing Characteristics
Table 10
lists processor bus input timings.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and
output delay with respect to the rising edge of a reference clock. The
reference clock is the FB_CLK output.
All other timing relationships can be derived from these values. Timings
listed in
Table 10
are shown in
Figure 11
and
Figure 12
.
Table 9. PLL Electrical Characteristics
Num
Characteristic
Symbol
Min.
Value
Max.
Value
Unit
1
PLL Reference Frequency Range
Crystal reference
External reference
f
ref_crystal
f
ref_ext
TBD
TBD
16
16
MHz
MHz
2
Core frequency
CLKOUT Frequency
1
NOTES:
1
All internal registers retain data at 0 Hz.
2
This parameter is guaranteed by characterization before qualification rather than 100% tested.
3
Proper PC board layout procedures must be followed to achieve specifications.
4
This parameter is guaranteed by design rather than 100% tested.
5
This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in
the synthesizer control register (SYNCR).
f
sys
f
sys/3
TBD
TBD
240
80
MHz
MHz
3
Crystal Start-up Time
2, 3
t
cst
10
ms
4
EXTAL Input High Voltage
Crystal Mode
4
All other modes (External, Limp)
V
IHEXT
V
IHEXT
TBD
TBD
TBD
TBD
V
V
5
EXTAL Input Low Voltage
Crystal Mode
4
All other modes (External, Limp)
V
ILEXT
V
ILEXT
TBD
TBD
TBD
TBD
V
V
6
XTAL Load Capacitance
2
5
30
pF
7
PLL Lock Time
2, 5
t
lpll
1
ms
8
Duty Cycle of reference
2
t
dc
40
60
%
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