MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3 F" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5272VM66J
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 533/544闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 66MHZ 196-MAPBGA
妯欐簴鍖呰锛� 126
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 66MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART锛孶SB
澶栧湇瑷倷锛� DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜鍣ㄥ閲忥細 16KB锛�4K x 32锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 ROM
RAM 瀹归噺锛� 1K x 32
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3 V ~ 3.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 鎵樼洡
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ColdFire Core
MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3
Freescale Semiconductor
2-21
Table 2-11 lists timings for MOVE.L.
Table 2-12 gives execution times for MOVE.L instructions accessing program-visible registers of the
MAC unit, along with other MOVE.L timings. Execution times for moving contents of the ACC or
MACSR into a destination location represent the best-case scenario when the store instruction is executed
and no load, MAC, or MSAC instructions are in the MAC execution pipeline. In general, these store
operations require only one cycle for execution, but if they are preceded immediately by a load, MAC, or
MSAC instruction, the MAC pipeline depth is exposed and execution time is three cycles.
Table 2-11. Move Long Execution Times
Source
Destination
Rx
(Ax)
(Ax)+
鈥�(Ax)
(d16,Ax)
(d8,Ax,Xi*SF)
(xxx).wl
Dy
1(0/0)
1(0/1)
2(0/1)
1(0/1)
Ay
1(0/0)
1(0/1)
2(0/1)
1(0/1)
(Ay)
2(1/0)
2(1/1)
3(1/1)
2(1/1)
(Ay)+
2(1/0)
2(1/1)
3(1/1)
2(1/1)
鈥�(Ay)
2(1/0)
2(1/1)
3(1/1)
2(1/1)
(d16,Ay)
2(1/0)
2(1/1)
鈥�
(d8,Ay,Xi*SF)
3(1/0)
3(1/1)
鈥�
(xxx).w
2(1/0)
2(1/1)
鈥�
(xxx).l
2(1/0)
2(1/1)
鈥�
(d16,PC)
2(1/0)
2(1/1)
鈥�
(d8,PC,Xi*SF)
3(1/0)
3(1/1)
鈥�
#<xxx>
1(0/0)
2(0/1)
鈥�
Table 2-12. Move Execution Times
Opcode
<ea>
Effective Address
Rn
(An)
(An)+
鈥�(An)
(d16,An)
(d8,An,Xi*SF)
(xxx).wl
#<xxx>
move.l
<ea>,ACC
1(0/0)
鈥�
1(0/0)
move.l
<ea>,MACSR
2(0/0)
鈥�
2(0/0)
move.l
<ea>,MASK
1(0/0)
鈥�
1(0/0)
move.l
ACC,Rx
1(0/0)
鈥�
move.l
MACSR,CCR
1(0/0)
鈥�
move.l
MACSR,Rx
1(0/0)
鈥�
move.l
MASK,Rx
1(0/0)
鈥�
鐩搁棞(gu膩n)PDF璩囨枡
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MCF5272VM66J 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:IC 32BIT MPU 66MHZ BGA-196
MCF5272VM66R2 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU MCF5272 V2CORE 4KSRAM RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰ㄦ牸:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MCF5272VM66R2 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:Microcontroler
MCF5272VM66R2J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 4KSRAM RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰ㄦ牸:SMD/SMT
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