MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3 1-6 Fr" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� MCF5272VM66J
寤犲晢锛� Freescale Semiconductor
鏂囦欢闋佹暩(sh霉)锛� 508/544闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC MCU 32BIT 66MHZ 196-MAPBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 126
绯诲垪锛� MCF527x
鏍稿績铏曠悊鍣細 Coldfire V2
鑺珨灏哄锛� 32-浣�
閫熷害锛� 66MHz
閫i€氭€э細 EBI/EMI锛屼互澶恫(w菐ng)锛孖²C锛孲PI锛孶ART/USART锛孶SB
澶栧湇瑷�(sh猫)鍌欙細 DMA锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 32
绋嬪簭瀛樺劜鍣ㄥ閲忥細 16KB锛�4K x 32锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 ROM
RAM 瀹归噺锛� 1K x 32
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 3 V ~ 3.6 V
鎸暕鍣ㄥ瀷锛� 澶栭儴
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 196-LBGA
鍖呰锛� 鎵樼洡
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Overview
MCF5272 ColdFire Integrated Microprocessor User鈥檚 Manual, Rev. 3
1-6
Freescale Semiconductor
1.2.2.4
Power Management
The sleep and stop power management modes reduce power consumption by allowing software to shut
down the core, peripherals, or the whole device during inactive periods. To reduce power consumption
further, software can individually disable internal clocks to the on-chip peripheral modules. The
power-saving modes are described as follows:
Sleep mode uses interrupt control logic to allow any interrupt condition to wake the processor. As
the MCF5272 is fully static, sleep mode is simply the disabling of the core鈥檚 clock after the current
instruction completes. An interrupt from any internal or external source causes on-chip power
management logic to reenable the core鈥檚 clock; execution resumes with the next instruction. This
allows rapid return from power-down state as compared to a dynamic implementation that must
perform power-on reset processing before software can handle the interrupt request. If interrupts
are enabled at the appropriate priority level, program control passes to the relevant interrupt service
routine.
Stop mode is entered by the disabling of the external clock input and is achieved by software setting
a bit in a control register. Program execution stops after the current instruction. In stop mode,
neither the core nor peripherals are active. The MCF5272 consumes very little power in this mode.
To resume normal operation, the external interrupts cause the power management logic to
re-enable the external clock input. The MCF5272 resumes program execution from where it
entered stop mode (if no interrupt are pending), or starts interrupt exception processing if interrupts
are pending.
1.2.2.5
Parallel Input/Output Ports
The MCF5272 has up to three 16-bit general-purpose parallel ports, each line of which can be programmed
as either an input or output. Some port lines have dedicated pins and others are shared with other MCF5272
functions. Some outputs have high drive current capability.
1.2.2.6
Interrupt Inputs
The MCF5272 has flexible latched interrupt inputs each of which can generate a separate, maskable
interrupt with programmable interrupt priority level and triggering edge (falling or rising). Each interrupt
has its own interrupt vector.
1.2.3
UART Module
The MCF5272 has two full-duplex UART modules with an on-chip baud rate generator providing both
standard and non-standard baud rates up to 5 Mbps. The module is functionally equivalent to the MC68681
DUART with enhanced features including 24-byte Tx and Rx FIFOs. Data formats can be 5, 6, 7, or 8 bits
with even, odd, or no parity and up to 2 stop bits in 1/16-bit increments. Receive and transmit FIFOs
minimize CPU service calls. A wide variety of error detection and maskable interrupt capability is
provided.
Using a programmable prescaler or an external source, the MCF5272 system clock supports various baud
rates. Modem support is provided with request-to-send (RTS) and clear-to-send (CTS) lines available
externally. Full-duplex autoecho loopback, local loopback, and remote loopback modes can be selected.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
MS3102E22-5S CONN RCPT 6POS BOX MNT W/SCKT
MS3112E12-10S CONN RECEPT 10POS W/SOCKT SOLDER
PS0055BE33036BF1 CAP CER 33PF 5KV 10% CHASSIS
PS0055BE27136BH1 CAP CER 270PF 5KV 10% CHASSIS
PS0055BE22136BH1 CAP CER 220PF 5KV 10% CHASSIS
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
MCF5272VM66J 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:IC 32BIT MPU 66MHZ BGA-196
MCF5272VM66R2 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU MCF5272 V2CORE 4KSRAM RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324
MCF5272VM66R2 鍒堕€犲晢:Freescale Semiconductor 鍔熻兘鎻忚堪:Microcontroler
MCF5272VM66R2J 鍔熻兘鎻忚堪:32浣嶅井鎺у埗鍣� - MCU V2CORE 4KSRAM RoHS:鍚� 鍒堕€犲晢:Texas Instruments 鏍稿績:C28x 铏曠悊鍣ㄧ郴鍒�:TMS320F28x 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:90 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:64 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:26 KB 鐗囦笂 ADC:Yes 宸ヤ綔闆绘簮闆诲:2.97 V to 3.63 V 宸ヤ綔婧害鑼冨湇:- 40 C to + 105 C 灏佽 / 绠遍珨:LQFP-80 瀹夎棰�(f膿ng)鏍�:SMD/SMT
MCF5274CVM166 鍔熻兘鎻忚堪:寰檿鐞嗗櫒 - MPU MCF5275 V2CORE RoHS:鍚� 鍒堕€犲晢:Atmel 铏曠悊鍣ㄧ郴鍒�:SAMA5D31 鏍稿績:ARM Cortex A5 鏁�(sh霉)鎿�(j霉)绺界窔瀵害:32 bit 鏈€澶ф檪閻橀牷鐜�:536 MHz 绋嬪簭瀛樺劜鍣ㄥぇ灏�:32 KB 鏁�(sh霉)鎿�(j霉) RAM 澶у皬:128 KB 鎺ュ彛椤炲瀷:CAN, Ethernet, LIN, SPI,TWI, UART, USB 宸ヤ綔闆绘簮闆诲:1.8 V to 3.3 V 鏈€澶у伐浣滄韩搴�:+ 85 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-324