
Signal Descriptions
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
19-18
Freescale Semiconductor
N11
CS3
—
CS3
Chip select 3
O
N12
DRESETEN
—
DRESETEN
DRAM controller reset
enable
I
N13
VDD
+3.3V
—
N14
HIZ
—
HiZ
High impedance enable
I
P1
PA7
QSPI_CS3
DOUT3
—
PA7/QSPI_CS3/DOUT3
PA7/QSPI chip select
4/PLIC port 3 data output
I/O
P2
High Z
—
DIN3
INT4
DIN3/INT4
Interrupt 4 input/PLIC
port 3 data input
I
P3
INT2
—
INT2
Interrupt input 1
I
P4
QSPI_Din
—
QSPI_Din
QSPI data input
I
P5
High Z
PWM_
OUT1
TOUT1
—
PWM_OUT1/TOUT1
PWM output compare 1
/Timer 1 output compare
O
P6
E_COL
—
E_COL
Collision
I
P7
E_RxD0
—
E_RxD0
Ethernet Rx data
I
P8
E_TxEN
—
E_TxEN
Ethernet Tx enable
O
P9
PB11
E_RxD3
—
PB11/E_RxD3
Port B bit 11/Rx data bit 3
(100 Base-T Ethernet
only)
I/O
P10
PB15
E_MDC
—
PB15/E_MDC
Port B bit 15/
Management Channel
Clock (100 Base-T only)
I/O
P11
CS2
—
CS2
Chip select 2
O
P12
CS6
—
CS6/AEN
Chip select 6
O
P13
OE/RD
—
OE/RD
Output enable/Read
O
P14
R/W
——
—
R/W
Read/Write
O
Table 19-2. Signal Name and Description by Pin Number (Sheet 8 of 8)
Map
BGA
Pin
Pin Functions
Name
Description
I/O
0 (Reset)
1
2
3