參數(shù)資料
型號(hào): MCF5234CVM100
廠商: MOTOROLA INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256
封裝: MAPBGA-256
文件頁(yè)數(shù): 48/76頁(yè)
文件大?。?/td> 2665K
代理商: MCF5234CVM100
52
MCF523x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
DC Electrical Specifications
6.3
DC Electrical Specifications
K = PD × (TA + 273 °C) + ΘJMA × PD
2 (3)
where K is a constant pertaining to the particular part. K can be determined from equation (3) by
measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be
obtained by solving equations (1) and (2) iteratively for any value of TA.
Table 44. DC Electrical Specifications 1
1
Refer to Table 45 for additional PLL specifications.
Characteristic
Symbol
Min
Max
Unit
Core Supply Voltage
VDD
1.35
1.65
V
Pad Supply Voltage
OVDD
3
3.6
V
Input High Voltage
VIH
0.7
× OV
DD
3.65
V
Input Low Voltage
VIL
VSS – 0.3
0.35
× OV
DD
V
Input Hysteresis
VHYS
0.06
× OV
DD
mV
Input Leakage Current
Vin = VDD or VSS, Input-only pins
Iin
–1.0
1.0
A
High Impedance (Off-State) Leakage Current
Vin = VDD or VSS, All input/output and output pins
IOZ
–1.0
1.0
A
Output High Voltage (All input/output and all output pins)
IOH = –5.0 mA
VOH
OVDD - 0.5
__
V
Output Low Voltage (All input/output and all output pins)
IOL = 5.0mA
VOL
__
0.5
V
Weak Internal Pull Up Device Current, tested at VIL Max.
2
Refer to the MCF5232 signals section for pins having weak internal pull-up devices.
IAPU
–10
– 130
A
Input Capacitance 3
All input-only pins
All input/output (three-state) pins
3
This parameter is characterized before qualification rather than 100% tested.
Cin
7
pF
Load Capacitance 4
Low drive strength
High drive strength
4
pF load ratings are based on DC loading and are provided as an indication of driver strength. High speed interfaces
require transmission line analysis to determine proper drive strength and termination. See High Speed Signal
Propagation: Advanced Black Magic by Howard W. Johnson for design guidelines.
CL
25
50
pF
Core Operating Supply Current 5
Master Mode
IDD
TBD
mA
Pad Operating Supply Current
Master Mode
Low Power Modes
OIDD
TBD
mA
A
DC Injection Current 3, 6, 7, 8
VNEGCLAMP =VSS– 0.3 V, VPOSCLAMP = VDD + 0.3
Single Pin Limit
Total processor Limit, Includes sum of all stressed pins
IIC
–1.0
–10
1.0
10
mA
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