參數(shù)資料
型號(hào): MCF5234CVM100
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256
封裝: MAPBGA-256
文件頁(yè)數(shù): 28/76頁(yè)
文件大?。?/td> 2665K
代理商: MCF5234CVM100
34
MCF523x Integrated Microprocessor Hardware Specifications
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Interface Recommendations
4.7.1.2
Address Multiplexing
Table 21 shows the generic address multiplexing scheme for SDRAM configurations. All possible address
connection configurations can be derived from this table.
Table 20. Synchronous DRAM Signal Connections
Signal
Description
SD_RAS
Synchronous row address strobe. Indicates a valid SDRAM row address is present and can be
latched by the SDRAM. SD_RAS should be connected to the corresponding SDRAM SD_RAS.
Do not confuse SD_RAS with the DRAM controller’s SD_CS[1:0], which should not be
interfaced to the SDRAM SD_RAS signals.
SD_CAS
Synchronous column address strobe. Indicates a valid column address is present and can be
latched by the SDRAM. SD_CAS should be connected to the corresponding signal labeled
SD_CAS on the SDRAM.
DRAMW
DRAM read/write. Asserted for write operations and negated for read operations.
SD_CS[1:0]
Row address strobe. Select each memory block of SDRAMs connected to the MCF523x. One
SD_CS signal selects one SDRAM block and connects to the corresponding CS signals.
SD_CKE
Synchronous DRAM clock enable. Connected directly to the CKE (clock enable) signal of
SDRAMs. Enables and disables the clock internal to SDRAM. When CKE is low, memory can
enter a power-down mode where operations are suspended or they can enter self-refresh
mode. SD_CKE functionality is controlled by DCR[COC]. For designs using external
multiplexing, setting COC allows SD_CKE to provide command-bit functionality.
BS[3:0]
Column address strobe. For synchronous operation, BS[3:0] function as byte enables to the
SDRAMs. They connect to the DQM signals (or mask qualifiers) of the SDRAMs.
CLKOUT
Bus clock output. Connects to the CLK input of SDRAMs.
Table 21. Generic Address Multiplexing Scheme
Address Pin Row Address Column Address
Notes Related to Port Sizes
17
0
8-bit port only
16
1
8- and 16-bit ports only
15
2
14
3
13
4
12
5
11
6
10
7
9
8
17
16
32-bit port only
18
17
16-bit port only or 32-bit port with only 8
column address lines
19
18
16-bit port only when at least 9 column
address lines are used
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