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參數(shù)資料
| 型號： | MCF5234CVM100 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 100 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | MAPBGA-256 |
| 文件頁數(shù)： | 14/76頁 |
| 文件大小： | 2665K |
| 代理商： | MCF5234CVM100 |
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MOTOROLA
MCF523x Integrated Microprocessor Hardware Specifications
21
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Primary Functions
Transfer Acknowledge
TA
Indicates that the external data transfer is complete. During a read
cycle, when the processor recognizes TA, it latches the data and then
terminates the bus cycle. During a write cycle, when the processor
recognizes TA, the bus cycle is terminated.
This pin can also be configured as GPIO.
I
Transfer Error
Acknowledge
TEA
Indicates an error condition exists for the bus transfer. The bus cycle
is terminated and the CPU begins execution of the access error
exception.
This pin can also be configured as GPIO or DMA transfer request
signal DREQ0.
I
Read/Write
R/W
Indicates the direction of the data transfer on the bus for SRAM (R/W)
and SDRAM (SD_WE) accesses. A logic 1 indicates a read from a
slave device and a logic 0 indicates a write to a slave device
This pin can also be configured as GPIO.
O
Transfer Size
TSIZ[1:0]
When the device is in normal mode, dynamic bus sizing lets the
programmer change data bus width between 8, 16, and 32 bits for
each chip select. The initial width for the bootstrap program chip
select, CS0, is determined by the state of TSIZ[1:0]. The program
should select bus widths for the other chip selects before accessing
the associated memory space. These pins our output pins.
These pins can also be configured as GPIO or DMA transfer
acknowledge signals DACK1/DACK0.
O
Transfer Start
TS
Bus control output signal indicating the start of a transfer.
This pin can also be configured as GPIO or DMA transfer
acknowledge signal DACK2.
O
Transfer in Progress
TIP
Bus control output signal indicating bus transfer in progress.
This pin can also be configured as GPIO or DMA transfer request
signal DREQ0.
O
Chip Selects
CS[7:0]
These output signals select external devices for external bus
transactions. The CS[3:2] can also be configured to function as
SDRAM chip selects SD_CS[1:0].
CS[7:1] pins can also be configured as GPIO.
O
Table 6. External Memory Interface Signals (continued)
Signal Name
Abbreviation
Function
I/O
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCF5235CVM150 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA256 |
| MCF5232CAB80 | 32-BIT, 80 MHz, RISC PROCESSOR, PQFP160 |
| MCF5232CVM100 | 32-BIT, 100 MHz, RISC PROCESSOR, PBGA196 |
| MCF5271CVM150 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA196 |
| MCF5270AB100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP160 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF5234CVM100J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF5234CVM150 | 功能描述:IC MPU 32BIT COLDFIRE 256-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:MCF523x 標(biāo)準(zhǔn)包裝:1 系列:AVR® ATmega 核心處理器:AVR 芯體尺寸:8-位 速度:16MHz 連通性:I²C，SPI，UART/USART 外圍設(shè)備:欠壓檢測/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（16K x 16） 程序存儲器類型:閃存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:44-TQFP 包裝:剪切帶 (CT) 其它名稱:ATMEGA324P-B15AZCT |
| MCF5234CVM150 | 制造商:Freescale Semiconductor 功能描述:Microprocessor IC |
| MCF5234CVM150J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:90 MHz 程序存儲器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF5235 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Integrated Microprocessor Hardware Specification |
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