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參數(shù)資料
| 型號(hào)： | MCF5232CAB80 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 80 MHz, RISC PROCESSOR, PQFP160 |
| 封裝： | QFP-160 |
| 文件頁數(shù)： | 14/76頁 |
| 文件大?。?/td> | 2665K |
| 代理商： | MCF5232CAB80 |
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MOTOROLA
MCF523x Integrated Microprocessor Hardware Specifications
21
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Signal Primary Functions
Transfer Acknowledge
TA
Indicates that the external data transfer is complete. During a read
cycle, when the processor recognizes TA, it latches the data and then
terminates the bus cycle. During a write cycle, when the processor
recognizes TA, the bus cycle is terminated.
This pin can also be configured as GPIO.
I
Transfer Error
Acknowledge
TEA
Indicates an error condition exists for the bus transfer. The bus cycle
is terminated and the CPU begins execution of the access error
exception.
This pin can also be configured as GPIO or DMA transfer request
signal DREQ0.
I
Read/Write
R/W
Indicates the direction of the data transfer on the bus for SRAM (R/W)
and SDRAM (SD_WE) accesses. A logic 1 indicates a read from a
slave device and a logic 0 indicates a write to a slave device
This pin can also be configured as GPIO.
O
Transfer Size
TSIZ[1:0]
When the device is in normal mode, dynamic bus sizing lets the
programmer change data bus width between 8, 16, and 32 bits for
each chip select. The initial width for the bootstrap program chip
select, CS0, is determined by the state of TSIZ[1:0]. The program
should select bus widths for the other chip selects before accessing
the associated memory space. These pins our output pins.
These pins can also be configured as GPIO or DMA transfer
acknowledge signals DACK1/DACK0.
O
Transfer Start
TS
Bus control output signal indicating the start of a transfer.
This pin can also be configured as GPIO or DMA transfer
acknowledge signal DACK2.
O
Transfer in Progress
TIP
Bus control output signal indicating bus transfer in progress.
This pin can also be configured as GPIO or DMA transfer request
signal DREQ0.
O
Chip Selects
CS[7:0]
These output signals select external devices for external bus
transactions. The CS[3:2] can also be configured to function as
SDRAM chip selects SD_CS[1:0].
CS[7:1] pins can also be configured as GPIO.
O
Table 6. External Memory Interface Signals (continued)
Signal Name
Abbreviation
Function
I/O
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MCF5232CVM100 | 32-BIT, 100 MHz, RISC PROCESSOR, PBGA196 |
| MCF5271CVM150 | 32-BIT, 150 MHz, RISC PROCESSOR, PBGA196 |
| MCF5270AB100 | 32-BIT, 100 MHz, RISC PROCESSOR, PQFP160 |
| MCF5272CVF66 | 32-BIT, 66 MHz, RISC PROCESSOR, PBGA196 |
| MCF5272VF66R2 | 32-BIT, 66 MHz, RISC PROCESSOR, PBGA196 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCF5232CVM100 | 功能描述:微處理器 - MPU MCF5232 V2CORE 64KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5232CVM100 | 制造商:Freescale Semiconductor 功能描述:Microprocessor IC |
| MCF5232CVM100J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
| MCF5232CVM150 | 功能描述:微處理器 - MPU MCF5232 V2CORE 64KSRAM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MCF5232CVM150J | 功能描述:32位微控制器 - MCU V2CORE 64KSRAM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT |
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