參數資料
型號: MCC3E0RX180WB0B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 180 MHz, RISC PROCESSOR, CBGA728
封裝: 29 X 29 MM, 4 MM HEIGHT, 1 MM PITCH, CERAMIC, FCBGA-728
文件頁數: 57/120頁
文件大?。?/td> 1633K
代理商: MCC3E0RX180WB0B
Pin Descriptions Grouped by Function
41
MOTOROLA GENERAL BUSINESS INFORMATION
C3ENPA1-DS/D REV 03
SONET OC-12 Transceiver Interface Configuration
SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a
CP within a cluster spends half its time performing receive functions, and the other half
performing transmit functions. Table 14 shows a CP Cluster configured for one OC-12
interface.
Table 14 OC-12 Signals Example
SIGNAL NAME*
PIN #
TOTAL
TYPE
I/O
LABEL
SIGNAL DESCRIPTION
CPn_0
1
LVTTL
O
PD
TCLK
Deskewed Transmit Clock (77.76MHz). This clock is used to
synchronize the transmit data.
CPn_1
1
LVTTL
I
PU
TCLKI
Transceiver Transmit Clock. This clock sets the frequency of the
transmit data and is typically sourced by the PHY chip.
CPn_2
1
LVTTL
O
PD
TXD(0)
Transmit Data (byte-wide data, least significant bit)
CPn_3
1
LVTTL
OPU
TXD(1)
Transmit Data
CPn_4
1
LVTTL
O
PD
TXD(2)
Transmit Data
CPn_5
1
LVTTL
O
PU
TXD(3)
Transmit Data
CPn_6
1
LVTTL
OPU
00F
Out of Frame
CPn+1_0
1
nc
PD
nc
CPn+1_1
1
nc
PU
nc
CPn+1_2
1
LVTTL
OPD
TXD(4)
Transmit Data
CPn+1_3
1
LVTTL
O
PU
TXD(5)
Transmit Data
CPn+1_4
1
LVTTL
O
PD
TXD(6)
Transmit Data
CPn+1_5
1
LVTTL
OPU
TXD(7)
Transmit Data (byte-wide data, most significant bit)
CPn+1_6
1
nc
PU
nc
CPn+2_0
1
nc
PD
nc
CPn+2_1
1
LVTTL
IPU
RCLK
Receive Clock (77.76MHz)
CPn+2_2
1
LVTTL
I
PD
RXD(0)
Receive Data (byte-wide receive data, least significant bit)
CPn+2_3
1
LVTTL
I
PU
RXD(1)
Receive Data
CPn+2_4
1
LVTTL
IPD
RXD(2)
Receive Data
CPn+2_5
1
LVTTL
I
PU
RXD(3)
Receive Data
CPn+2_6
1
LVTTL
I
PU
FP
Frame Synchronization Pulse. This is valid during the third A2 of
the receive SONET frame.
CPn+3_0
1
nc
PD
nc
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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