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參數(shù)資料
| 型號： | MC9328MX21DVG |
| 廠商： | Motorola, Inc. |
| 英文描述： | i.MX family of microprocessors |
| 中文描述： | i.MX系列微處理器 |
| 文件頁數(shù)： | 82/96頁 |
| 文件大小： | 1495K |
| 代理商： | MC9328MX21DVG |
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MC9328MX1 Advance Information, Rev. 4
82
Freescale Semiconductor
Specifications
3.20 I
2
C Module
The I
2
C communication protocol consists of seven elements: START, Data Source/Recipient, Data Direction,
Slave Acknowledge, Data, Data Acknowledge, and STOP.
Figure 63. Definition of Bus Timing for I
2
C
3.21 Synchronous Serial Interface
The MC9328MX1 processor contains two identical SSI modules. The transmit and receive sections of the SSI can
be synchronous or asynchronous. In synchronous mode, the transmitter and the receiver use a common clock and
frame synchronization signal. In asynchronous mode, the transmitter and receiver each have their own clock and
frame synchronization signals. Continuous or gated clock mode can be selected. In continuous mode, the clock
runs continuously. In gated clock mode, the clock functions only during transmission. The internal and external
clock timing diagrams are shown in Figure 65 through Figure 67 on page 84.
Normal or network mode can also be selected. In normal mode, the SSI functions with one data word of
I/O per frame. In network mode, a frame can contain between 2 and 32 data words. Network mode is typically used
in star or ring-time division multiplex networks with other processors or codecs, allowing interface to time division
multiplexed networks without additional logic. Use of the gated clock is not allowed in network mode. These
distinctions result in the basic operating modes that allow the SSI to communicate with a wide variety of devices.
Table 39. I
2
C Bus Timing Parameter Table
Ref
No.
Parameter
1.8V +/- 0.10V
3.0V +/- 0.30V
Unit
Minimum
Maximum
Minimum
Maximum
1
Hold time (repeated) START condition
182
–
160
–
ns
2
Data hold time
0
171
0
150
ns
3
Data setup time
11.4
–
10
–
ns
4
HIGH period of the SCL clock
80
–
120
–
ns
5
LOW period of the SCL clock
480
–
320
–
ns
6
Setup time for STOP condition
182.4
–
160
–
ns
SDA
SCL
1
2
3
4
6
5
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相關代理商/技術參數(shù) |
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|---|---|
| MC9328MX21DVGR2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC9328MX21DVH | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:i.MX family of microprocessors |
| MC9328MX21DVK | 功能描述:處理器 - 專門應用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
| MC9328MX21DVK | 制造商:Freescale Semiconductor 功能描述:Microprocessor |
| MC9328MX21DVKR2 | 功能描述:處理器 - 專門應用 DB I.MX21 PB-FR RoHS:否 制造商:Freescale Semiconductor 類型:Multimedia Applications 核心:ARM Cortex A9 處理器系列:i.MX6 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:1 GHz 指令/數(shù)據(jù)緩存: 數(shù)據(jù) RAM 大小:128 KB 數(shù)據(jù) ROM 大小: 工作電源電壓: 最大工作溫度:+ 95 C 安裝風格:SMD/SMT 封裝 / 箱體:MAPBGA-432 |
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