參數(shù)資料
型號(hào): MC9328MX21DVG
廠商: Motorola, Inc.
英文描述: i.MX family of microprocessors
中文描述: i.MX系列微處理器
文件頁數(shù): 24/96頁
文件大小: 1495K
代理商: MC9328MX21DVG
MC9328MX1 Advance Information, Rev. 4
24
Freescale Semiconductor
Specifications
3.9.1 DTACK Signal Description
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal as a
data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not terminated by the
external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group supports DTACK signal
function when the external DTACK signal is used for data acknowledgement.
3.9.2 DTACK Signal Timing
Figure 6 through Figure 9 show the access cycle timing used by chip-select 5. The signal values and units of
measure for this figure are found in the associated tables.
3.9.2.1 DTACK READ Cycle without DMA
Figure 6. DTACK READ Cycle without DMA
Table 14. Parameters for Read Cycle, WSC = 111111, DTACK_SEL=0, HKCL=96MHz
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
1
OE and EB assertion time
See note 2
ns
2
CS5
pulse width
3T
ns
3
OE
negated to address inactive
46.44
ns
4
DTACK
asserted after CS5 asserted
1019T
ns
DTACK
Address
EB
CS5
OE
Databus
input to MX1)
programmable
min 0ns
(1)
(5)
(6)
(3)
(2)
(4)
(7)
(8)
(9)
(10)
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