參數(shù)資料
型號： MC9328MX21DVG
廠商： Motorola, Inc.
英文描述： i.MX family of microprocessors
中文描述： i.MX系列微處理器
文件頁數(shù)： 26/96頁
文件大小： 1495K
代理商： MC9328MX21DVG
MC9328MX1 Advance Information, Rev. 4
26
Freescale Semiconductor
Specifications
Table 15. Parameters for Read Cycle WSC = 111111, DTACK_SEL=0, HCLK=96MHz
Number
Characteristic
(3.0 ± 0.3) V
Unit
Minimum
Maximum
1
OE and EB assertion time
See note 2
–
ns
2
CS pulse width
3T
–
ns
3
OE negated before CS5 is negated
0.5T+0.24
0.5T+0.67
ns
4
Address inactive before CS negated
–
0.93
ns
5
DTACK
asserted after CS5 asserted
–
1019T
ns
6
DTACK
asserted to OE negated
3T+2.2
4T+6.86
ns
7
Data hold timing after OE negated
0
–
ns
8
Data ready after DTACK is asserted
–
T
ns
9
CS deactive to next CS active
T
–
ns
10
OE negate after EB negate
0.5
1.5
ns
11
DTACK
pulse width
1T
3T
ns
Note
:
0. DTACK assert mean DTACK become low.
1. T is the system clock period. (For 96MHz system clock)
2. OE and EB assertion time is programmable by OEA bit in CS5L register. EB
assertion in read cycle will occur only
when EBC bit in CS5L register is clear.
3. Address becomes valid and CS asserts at the start of read access cycle.
4. The external DTACK input requirement is eliminated when CS5 is programmed to use internal wait state.
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參數(shù)描述
MC9328MX21DVGR2 制造商:Rochester Electronics LLC 功能描述:- Bulk
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