參數(shù)資料
型號(hào): MC9328MX21DVG
廠商: Motorola, Inc.
英文描述: i.MX family of microprocessors
中文描述: i.MX系列微處理器
文件頁(yè)數(shù): 61/96頁(yè)
文件大?。?/td> 1495K
代理商: MC9328MX21DVG
Specifications
MC9328MX1 Advance Information, Rev. 4
Freescale Semiconductor
61
Figure 42. Master SPI Timing Diagram Ignore SPI_RDY Level Trigger
Figure 43. Slave SPI Timing Diagram FIFO Advanced by BIT COUNT
Figure 44. Slave SPI Timing Diagram FIFO Advanced by SS Rising Edge
Table 26. Timing Parameter Table for Figure 40 through Figure 44
Ref
No.
Parameter
Minimum
Maximum
Unit
1
SPI_RDY to SS output low
2T
1
1.
2.
3.
T = CSPI system clock period (PERCLK2).
Tsclk = Period of SCLK.
WAIT = Number of bit clocks (SCLK) or 32.768 KHz clocks per Sample
Period Control Register.
ns
2
SS output low to first SCLK edge
3·Tsclk
2
ns
3
Last SCLK edge to SS output high
2·Tsclk
ns
4
SS output high to SPI_RDY low
0
ns
5
SS output pulse width
Tsclk + WAIT
3
ns
6
SS input low to first SCLK edge
T
ns
7
SS input pulse width
T
ns
SCLK, MOSI, MISO
SS (output)
SS (input)
SCLK, MOSI, MISO
6
7
SS (input)
SCLK, MOSI, MISO
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