參數(shù)資料
型號(hào)： MC7410VU500LE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 30/56頁(yè)
文件大小： 0K
描述： IC MPU RISC 32BIT 360-FCCBGA
標(biāo)準(zhǔn)包裝： 44
系列： MPC74xx
處理器類(lèi)型： 32-位 MPC74xx PowerPC
速度： 500MHz
電壓： 1.8V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 360-BCBGA，F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝： 360-FCCBGA（25x25）
包裝： 托盤(pán)
MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
36
Freescale Semiconductor
System Design Information
MPC7410 core, and the phase adjustment range that the L2 DLL supports. Table 14 shows various example L2 clock
frequencies that can be obtained for a given set of core frequencies. The minimum L2 frequency target is 133 MHz.
Sample core-to-L2 frequencies for the MPC7410 is shown in Table 14. In this example, shaded cells represent
settings that, for a given core frequency, result in L2 frequencies that do not comply with the minimum and
maximum L2 frequencies listed in Table 10.
8.2 PLL and DLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the MPC7410 to supply power to the PLL and DLL,
respectively. Both AVDD and L2AVDD can be supplied power from the VDD power plane. High frequency noise in
the 500 kHz to 10 MHz resonant frequency range of the PLL on the VDD power plane could affect the stability of
the internal clocks.
On systems that use the MPC7410 HCTE device, the AVDD and L2AVDD input signals should both implement the
circuit shown in Figure 21.
On systems that use the MPC7410 CBGA device, the L2AVDD input should implement the circuit shown in
When selecting which filter to use on the AVDD input of the MPC7410 CBGA device specifically, system designers
should refer to Erratum No. 18 in the MPC7410 RISC Microprocessor Chip Errata (MPC7410CE). The AVDD input
of the MPC7410 CBGA device is sensitive to system noise on both the VDD power plane, as described above, and
the OVDD power plane as described in the Erratum No. 18. With these AVDD sensitivities to OVDD and VDD noise,
care must be taken when selecting the filter circuit for the AVDD input of the MPC7410 CBGA device. Erratum
No. 18 does not apply to the AVDD input of the MPC7401 HCTE device, nor does it affect the L2AVDD input of
either the HCTE or the CBGA device.
As described in Erratum No. 18, when there is a high amount of noise on the OVDD power plane due to I/O switching
rates, it is possible for the OVDD noise to couple into the PLL supply voltage (AVDD) internal to the MPC7410
CBGA package. It is the recommendation of Freescale, that new designs using the MPC7410 CBGA package
provide the ability to implement either filter shown in Figure 21 and Figure 22 at the AVDD input. Existing designs
that implemented Figure 21 on AVDD may never experience the error described in Erratum No. 18. Both new and
Table 14. Sample Core-to-L2 Frequencies
Core Frequency
(MHz)
÷1
÷1.5
÷2
÷2.5
÷3
÷3.5
÷4
350
233
175
140
—
366
244
183
147
—
400
266
200
160
133
—
433
—
288
216
173
144
—
450
—
300
225
180
150
—
466
—
311
233
186
155
133
—
500
—
333
250
200
166
143
—
Note: The core and L2 frequencies are for reference only. Some examples may
represent core or L2 frequencies which are not useful, not supported, or not tested
for by the MPC7410; see Section 4.2.3, “L2 Clock AC Specifications,” for valid
L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less
than 150 MHz.
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