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參數(shù)資料
| 型號： | MC7410VU400NE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 44/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU RISC 32BIT 360-FCCBGA |
| 標準包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 400MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-BCBGA，F(xiàn)CCBGA |
| 供應商設備封裝： | 360-FCCBGA（25x25） |
| 包裝： | 托盤 |
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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
Freescale Semiconductor
49
Document Revision History
5
4/13/2005
Section numbering revised. In all previous versions, section numbering began with ‘1.’ These extra
‘1’s’ were deleted. For example, previously numbered section 1.8.2 changed to 8.2.
Section 7.1—added CTE value for HCTE package. Corrected minimum module height from 2.65 mm
to 2.72 mm per Figure 17.
Section 3—added HCTE_LGA (VS package descriptor) package description which is the
HCTE_CBGA (HX package descriptor) with the spheres removed.
Table 4—generalized ‘HCTE CBGA’ column to ‘HCTE’ to include both HCTE_CBGA and HCTE_LGA
package thermal characteristics.
Section 5—added HCTE_LGA package. The HCTE_LGA has the same pin assignments as the
CBGA and HCTE_CBGA packages. Added side view Part C for HCTE_LGA.
Section 6—added HCTE_LGA package (VS package descriptor). The HCTE_LGA has the same
pinout listing as the CBGA and HCTE packages.
Section 7.3—added HCTE_LGA package parameters.
Section 7.4—added HCTE_LGA package mechanical dimensions.
Table 17—added HCTE_LGA package (VS package descriptor) to part numbering nomenclature.
4
—
Table 5—Changed measurement test condition IOH from -6mA to –5 mA for VOH and IOL from 6 mA
to 5 mA for VOL per Product Bulletin.
Section 1.8.2—revised text regarding AVDD filter selection for the CBGA package.
3
—
Table 6—Changed note 1 to specify that OVDD and L2OVDD power is typically <5% of VDD power.
Figure 17—revised diagram and dimensions to specify ‘cap regions’ versus individual cap
measurements. Moved individual capacitor placement to separate figure.
Figure 18—Added this figure to show each individual capacitor placement and value.
Figure 22—updated COP Connector Diagram to recommend a weak pull-up resistor on TCK.
2
—
Public release, includes Rev 1.1 changes.
Section 1.7.2—added package capacitor values.
Section 1.8.6—added recommendation that strong pull-up/down resistors be used on the
PLL_CFG[0:3] signals.
Table 8—removed mode input setup and hold times. These inputs adhere to the general input setup
and hold specifications.
Figure 5—revised mode input diagram to show sample points around HRESET negation.
Section 1.3—added HCTE package description.
Figure 22—added note 6 to emphasize that COP emulator and target board need to be able to drive
HRESET and TRST independently to the CPU.
Section 1.8.2—revised section for HCTE package. Added text and figure for AVDD filter for the CBGA
package.
Section 1.8.6—removed AACK, TEA, and TS from control signals requiring pull-ups. Removed TBST
from snooped transfer attribute list. TBST is an output and is not snooped.
Table 16. Document Revision History (continued)
Revision
Date
Substantive Change(s)
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