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| 型號： | MC7410VU400NE |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 21/56頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU RISC 32BIT 360-FCCBGA |
| 標(biāo)準(zhǔn)包裝： | 44 |
| 系列： | MPC74xx |
| 處理器類型： | 32-位 MPC74xx PowerPC |
| 速度： | 400MHz |
| 電壓： | 1.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 360-BCBGA，F(xiàn)CCBGA |
| 供應(yīng)商設(shè)備封裝： | 360-FCCBGA（25x25） |
| 包裝： | 托盤 |
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MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1
28
Freescale Semiconductor
Pinout Listings
VDD
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12
—
N/A
—
Notes:
1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and
L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:18], L2DATA[0:63], L2DP[0:7], and L2SYNC_OUT)
and the L2 control signals; and VDD supplies power to the processor core and the PLL and DLL (after filtering to become
AVDD and L2AVDD, respectively). These columns serve as a reference for the nominal voltage supported on a given signal
as selected by the BVSEL/L2VSEL pin configurations of Table 2 and the voltage supplied. For actual recommended value
2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation.
3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OVDD,
GND, HRESET, or HRESET. For the MPC7410 the L2 bus only supports 2.5- and 1.8-V options. The default selection, if
L2VSEL is left unconnected, is 2.5-V operation. For the MPC7410 the processor bus supports 3.3-, 2.5-, and 1.8-V options.
The default selection, if BVSEL is left unconnected, is 3.3-V operation. Refer to Table 2 for supported BVSEL and L2VSEL
settings.
4. PLL_CFG[0:3] must remain stable during operation; should only be changed during the assertion of HRESET or during sleep
mode and must adhere to the internal PLL-relock time requirement.
5. Ignored input in 60x bus mode.
6. Unused output in 60x bus mode. Signal is three-stated in 60x mode.
7. Deasserted (pulled high) at HRESET negation for 60x bus mode. Asserted (pulled low) at HRESET negation for MPX bus
mode.
8. Uses one of nine existing no connects in the MPC750 360 BGA package.
9. Internal pull up on die. Pulled-up signals are VDD based.
10.Reuses MPC750 DRTRY, DBDIS, and TLBISYNC pins (DTI1, DTI2, and EMODE, respectively).
11.The VOLTDET pin position on the MPC750 360 BGA package is now an L2OVDD pin on the MPC7410 360 package.
12.Output only for MPC7410, was I/O for MPC750.
13.MPX bus mode only.
14.If necessary, to overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down
resistance less than 250
Ω should be used.
15.MCP minimum pulse width: asynchronous, falling-edge input needs to be held asserted for a minimum of 2 cycles to
guarantee that it is latched by the processor.
16.In MPX bus mode the ABB signal is called AMON and the DBB signal is called DMON. These signals are not a requirement
of the MPX bus protocol and may not be available on future products.
Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)
Signal Name
Pin Number
Active
I/O
I/F Select 1
Notes
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