參數(shù)資料
型號: MC705L16CFUE
廠商: Freescale Semiconductor
文件頁數(shù): 99/146頁
文件大?。?/td> 0K
描述: IC MCU 8BIT EPROM 80-QFP
標(biāo)準(zhǔn)包裝: 84
系列: HC05
核心處理器: HC05
芯體尺寸: 8-位
速度: 2.1MHz
連通性: SPI
外圍設(shè)備: LCD,POR,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: OTP
RAM 容量: 512 x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 5.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-QFP
包裝: 托盤
Parallel Input/Output (I/O)
MC68HC05L16 MC68HC705L16 Data Sheet, Rev. 4.1
56
Freescale Semiconductor
6.5.1 Port D Data Register
Read
Anytime; returns output data latch; bit 0 is always read logic 1
Write
Anytime (Writes do not change pin state when configured for LCD driver output.)
Reset
All bits set to logic 1 and output ports disconnected from the pins (LCD is enabled on reset.)
6.5.2 Port D MUX Register
Read
Anytime (When OPTM = 1, bits 3–0 always read logic 0.)
Write
Anytime (Writes have no effect if PDH is set.)
Reset
All bits cleared; LCD enabled
PDMx — Port D MUX Control bit x
0 = Configure pin PDx to LCD
1 = Configure pin PDx to output
6.6 Port E
Port E pins serve one of two basic functions depending on the MCU mode selected:
LCD frontplane driver outputs
General-purpose output pins
Since port E is an output-only port, there is no DDRE register. Instead of DDRE, port E MUX control
register (PEMUX) is used. Bits 7–0 of this register control the port/LCD muxing of port E bits 7–0
respectively on a bit-wide basis. These bits are cleared on reset, and writing a logic 1 to any bit will turn
that pin into a port output. This function is superseded by the PEH and PEL bits in the LCD control register.
When PEH is set, the upper four bits of port E become port outputs regardless of the state of the PEMUX
bits. Likewise, when PEL is set, the lower four bits of port E become outputs.
Address:
$0003
Bit 7
654321
Bit 0
Read:
PD7
PD6
PD5
PD4
PD3
PD2
PD1
1
Write:
Reset:
11111111
Figure 6-7. Port D Data Register (PORTD)
Address:
Option Map — $0003
Bit 7
654321
Bit 0
Read:
PDM7
PDM6
PDM5
PDM4
0000
Write:
Reset:
00000000
Figure 6-8. Port D MUX Register (PDMUX)
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