參數(shù)資料
型號: MC68HC705SB7
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 18/170頁
文件大?。?/td> 2161K
代理商: MC68HC705SB7
GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
ANALOG SUBSYSTEM
MC68HC05SB7
15-16
REV 2.1
ICEN
This is a read/write bit that enables a voltage comparison to trigger the input
capture register of the programmable Timer when the CPF ag bit is set. There-
fore an A/D conversion could be started by receiving an OCF or TOF from the
programmable Timer; and then terminated when the voltage on the external
ramping capacitor reaches the level of the unknown voltage. The time of termi-
nation will be stored in the 16-bit buffer located at $0014 and $0015. This bit is
automatically set whenever Mode 2 or 3 is selected by setting the ATD2 control
bit. This bit is cleared by a reset of the device.
1 =
Connects the CPF ag bit to the Timer input capture register.
0 =
Connects the PB1/TCAP pin to the Timer input capture register.
NOTE
When the ICEN bit is set the input capture function of the programmable Timer is
not connected to the PB1/TCAP pin but is driven by the CPF output ag from the
comparator. To return to capturing times from external events, the ICEN bit must
rst be cleared before the timed event occurs.
NOTE
The TCSEL bit in the Miscellaneous Control Register (bit 2 in $0B) must be
cleared for ICEN control. TCSEL=1 will select the SCL signal from the SMBus as
16-bit Timer Input Capture source, irrespective of ICEN setting.
CPIE
This is a read/write bit that enables an analog interrupt when the CPF ag bits
is set to a logical one. This bit is cleared by a reset of the device.
1 =
Enables analog interrupt when comparator ag bit is set.
0 =
Disables analog interrupt when comparator ag bit is set.
3
Automatic
Charge and
Discharge
(OCF-ICF)
Synchronized
to Timer
1110
The CHG bit remains cleared as long as current
is being sunk. Begin sourcing current when the
next Timer OCF occurs.
1111
The CHG bit remains set as long as current is
being sourced. Begin sinking current when the
next Timer ICF occurs.
Table 15-3. A/D Conversion Options
A/D
Option
Mode
Charge
Control
A/D Options
Current Flow To/From CAP
ISEN
ATD2
ATD1
CHG
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