參數(shù)資料
型號(hào)： MC68HC705SB7
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 158/170頁
文件大?。?/td> 2161K
代理商： MC68HC705SB7
GENERAL RELEASE SPECIFICATION
August 27, 1998
MOTOROLA
SM-BUS
MC68HC05SB7
12-10
REV 2.1
12.5.5 SM-Bus Data I/O Register (SMDR)
In master transmit mode, data written to this register is sent (MSB rst) to the bus
automatically. In master receive mode, reading from this register initiates receiving
of the next byte of data. In slave mode, the same function is available after it is
addressed.
12.5.6 SM-Bus logic Level
Two choices of logic level is available for the SM-Bus: TTL or CMOS.
SMINLEV — SM-Bus Input Level Select
This read/write bit selects whether SM-Bus input level is TTL or CMOS. Reset
clears the SMINLEV bit.
1 =
TTL input level is selected.
0 =
CMOS input level is selected.
12.5.7 SCL as16-bit Timer Input Capture
The SCL signal can be routed to the 16-bit Timer Input Capture by setting the
TCSEL bit in the Miscellaneous Control Register.
TCSEL — 16-bit Timer Input Capture Source Select
This read/write bit selects the input capture source to the 16-bit Timer. Reset
clears TCSEL.
1 =
SM-Bus SCL is routed to input capture of 16-bit Timer.
0 =
CPF or external TCAP pin (depends on the state of ICEN bit in ACR,
$1D) is routed to 16-bit Timer.
See section Input Capture of 16-bit Timer for more details.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SMDR
R
SMD7
SMD6
SMD5
SMD4
SMD3
SMD2
SMD1
SMD0
$0024
W
reset:
00000000
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MCR
R
TSEN
LVRON
0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
$000B
W
COPON
reset:
01000000
Figure 12-4. Miscellaneous Control Register (MCR)
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