參數(shù)資料
型號: MC68HC16Y1
廠商: Motorola, Inc.
英文描述: 16-Bit Modular Microcontroller(16位模塊化微控制器)
中文描述: 16位微控制器模塊(16位模塊化微控制器)
文件頁數(shù): 65/122頁
文件大小: 749K
代理商: MC68HC16Y1
MC68HC16Y1
MC68HC16Y1TS/D
MOTOROLA
65
Because ADDR20 = ADDR19 in the CPU16, maximum block size is 512 Kbytes. Because ADDR[23:20]
follow the logic state of ADDR19, if all 24 address lines are used, addresses from $080000 to $F7FFFF
are inaccessible.
3.10.4 Option Registers
The option registers contain eight fields that determine timing of and conditions for assertion of chip se-
lect signals. These make the chip selects useful for generating peripheral control signals. Certain con-
straints set by fields in the base address register and in the option register must be satisfied in order to
assert a chip select signal, and to provide DSACK or autovector support.
The option register for CSBOOT, CSORBT, contains special reset values that support bootstrap opera-
tions from peripheral memory devices.
MODE — Asynchronous/Synchronous Mode
0 = Asynchronous mode selected
1 = Synchronous mode selected
In asynchronous mode, the chip select is asserted synchronized with AS or DS.
In synchronous mode, the DSACK field is not used, because a bus cycle is only performed as a syn-
chronous operation. When a match condition occurs on a chip select programmed for synchronous op-
eration, the chip select signals the EBI that an E-clock cycle is pending.
BYTE — Upper/Lower Byte Option
This field is used only when the chip select 16-bit port option is selected in the pin assignment register.
The following table lists upper/lower byte options.
R/W — Read/Write
This field causes a chip select to be asserted only for a read, only for a write, or for both read and write.
The table below shows the options.
CSORBT
— Chip Select Option Register Boot ROM
$YFFA4A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
AVEC
RESET:
0
1
1
1
1
0
1
1
0
1
1
1
0
0
0
0
CSOR0 – CSOR10
— Chip Select Option Registers
$YFFA4E–$YFFA76
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MODE
BYTE
R/W
STRB
DSACK
SPACE
IPL
AVEC
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Byte
00
01
10
11
Description
Disable
Lower Byte
Upper Byte
Both Bytes
R/W
00
01
10
11
Description
Reserved
Read Only
Write Only
Read/Write
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