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| 型號： | MC68HC11FC0CFU5 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Technical Summary 8-Bit Microcontroller |
| 中文描述： | 8-BIT, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 51/74頁 |
| 文件大小： | 513K |
| 代理商： | MC68HC11FC0CFU5 |
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MC68HC11F1/FC0
MOTOROLA
MC68HC11FTS/D
55
11.3 A/D Registers
I = Indeterminate value
CCF — Conversions Complete Flag
A read-only status indicator, this bit is set when all four A/D result registers contain valid conversion re-
sults. Each time the ADCTL register is overwritten, this bit is automatically cleared to zero and a con-
version sequence is started. In the continuous mode, CCF is set at the end of the first conversion
sequence.
Bit 6 — Not implemented. Reads always return zero and writes have no effect.
SCAN — Continuous Scan Control
0 = Do four conversions and stop
1 = Convert four channels in selected group continuously
MULT — Multiple Channel/Single Channel Control
0 = Convert single channel selected
1 = Convert four channels in selected group
CD–CA — Channel Select D through A
Refer to Table 24. When a multiple channel mode is selected (MULT = 1), the two least significant chan-
nel select bits (CB and CA) have no meaning and the CD and CC bits specify which group of four chan-
nels is to be converted.
NOTES:
1. Used for factory testing.
ADCTL — A/D Control/Status
$x030
Bit 7
6
5
4
3
2
1
Bit 0
CCF
0
SCAN
MULT
CD
CC
CB
CA
RESET:
I
0
I
Table 24 A/D Converter Channel Assignments
Channel Select Control Bits
CD:CC:CB:CA
Channel Signal
Result in ADRx if MULT = 1
0000
AN0
ADR1
0001
AN1
ADR2
0010
AN2
ADR3
0011
AN3
ADR4
0100
AN4
ADR1
0101
AN5
ADR2
0110
AN6
ADR3
0111
AN7
ADR4
10XX
Reserved
ADR1–ADR4
1100
VRH
1
ADR1
1101
VRL
ADR2
1110
(VRH)/2
ADR3
1111
ADR4
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