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參數(shù)資料
| 型號： | MC68HC11FC0CFU5 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Technical Summary 8-Bit Microcontroller |
| 中文描述： | 8-BIT, 6 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁數(shù)： | 46/74頁 |
| 文件大?。?/td> | 513K |
| 代理商： | MC68HC11FC0CFU5 |
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MOTOROLA
MC68HC11F1/FC0
50
MC68HC11FTS/D
10.2 SPI Registers
U = Unaffected by reset
SPIE — SPI Interrupt Enable
When SPI interrupts are enabled, a hardware interrupt sequence is requested each time the SPIF or
MODF status flag is set. SPI interrupts are inhibited if this bit is cleared or if the I bit in the condition code
register is one.
0 = SPI interrupt disabled
1 = SPI interrupt enabled
SPE — SPI Enable
When the SPE bit is set, PD[5:2] are dedicated to the SPI function. If the SPI is in master mode and the
DDRD bit 5 is set, then PD5/SS becomes a general-purpose output instead of the SS input.
0 = SPI off
1 = SPI on
DWOM — Port D Wired-OR Mode Option for SPI Pins PD[5:2]
0 = Normal CMOS outputs
1 = Open-drain outputs
MSTR — Master Mode Select
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master device
has a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 13.
CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between mas-
ter and slave. The CPHA bit selects one of two clocking protocols. Refer to Figure 13.
Figure 13 SPI Data Clock Timing Diagram
SPCR — SPI Control Register
$x028
Bit 7
6
5
4
3
2
1
Bit 0
SPIE
SPE
DWOM
MSTR
CPOL
CPHA
SPR1
SPR0
RESET:
0
1
U
SCK CYCLE #
(FOR REFERENCE)
12345678
SCK (CPOL = 0)
SCK (CPOL = 1)
(CPHA = 0) DATA OUT
(CPHA = 1) DATA OUT
SS (TO SLAVE)
SAMPLE INPUT
MSB
654321
LSB
MSB
654321
LSB
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