
M68HC11
REFERENCE MANUAL
ANALOG-TO-DIGITAL CONVERTER SYSTEM
MOTOROLA
12-17
control logic, which forces unusual connections of the DAC capacitors during sample
time. Thus, the charge attained will be identical to that obtained by sampling an analog
level of 1/2 V
RH
on one of the eight analog input pins.
12.2.5 A/D Result Registers (ADR[4:1])
The A/D result registers are read-only registers used to hold an 8-bit conversion result.
After all four result registers have been filled with valid data in a conversion sequence,
the CCF status bit is set to indicate the results are valid. New conversion results are
calculated in the A/D logic and are transferred into the result registers in a part of the
clock cycle where reads do not take place; therefore, no interference occurs between
software reads and result updates.
12.3 A/D Pin Connection Considerations
Since there are no P-channel devices directly connected to the A/D input or reference
pins, voltages above V
DD
do not pose a latchup threat. If an A/D input rises above the
threshold of the protection device, an input protection device avalanches, and current
into this device should be limited. Because of an inherent diode to V
SS
, A/D inputs
must not go below V
SS
, or the input can be permanently damaged. A series resistor of
1 k
will prevent damage, but avoid a series resistor of more than 10 k
because input
leakage acting through this impedance will degrade A/D accuracy. External clamping
diodes on A/D inputs should be avoided because the leakage through these devices
is greater than the input pin leakage current and could significantly degrade accuracy
if significant resistance exists in series with the analog source.
Figure 12-5
shows a
model of an A/D input pin, which is useful in planning external circuitry and connec-
tions.
Figure 12-5 Electrical Model of an A/D Input Pin (Sample Mode)
Capacitors from A/D inputs to V
RL
help prevent errors due to system noise, but it is
important to size these capacitors properly for the way the A/D converter is being used
in a particular system. Factors affecting the size of these capacitors are as follows:
1. Source impedance of the analog signal
2. Rate of change of the analog signal
DIFFUSION/POLY
COUPLER
< 2 pF
400 nA
JUNCTION
LEAKAGE
+ ~20V
– ~0.7V
*
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
V
RL
INPUT
PROTECTION
DEVICE
+ ~12V
– ~0.7V
≤
4 K
DUMMY N-CHANNEL
OUTPUT DEVICE
ANALOG
INPUT
PIN
~ 20 pF
DAC
CAPACITANCE