參數(shù)資料
型號: MC68HC05X4CDWR2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.2 MHz, MICROCONTROLLER, PDSO28
封裝: PLASTIC, SOIC-28
文件頁數(shù): 164/168頁
文件大?。?/td> 656K
代理商: MC68HC05X4CDWR2
Motorola CAN
Interface to the MC68HC05X4 CPU
MC68HC05X4 Rev 1.0
MOTOROLA
Motorola CAN
95
27-mcan
Remote
transmission
request and data
length code
register (TRTDL)
ID2 – ID0 — Identifier bits
These bits contain the least significant bits of the transmit buffer
identifier.
RTR — Remote transmission request
1 = A remote frame will be transmitted.
0 = A data frame will be transmitted.
DLC3 – DLC0 — Data length code bits.
The data length code contains the number of bytes (data byte count)
of the respective message. At transmission of a remote frame, the
data length code is ignored, forcing the number of bytes to be 0. The
data byte count ranges from 0 to 8 for a data frame. Table 6 shows
the effect of setting the DLC bits.
Address:
$002B
Bit 7
654321
Bit 0
ID10
ID9
ID8
ID7
ID6
ID5
ID4
ID3
Reset:
Undened
Figure 16. RTR and Data Length Code Register (TRTDL)
Table 6. Data length codes
Data length code
Data byte
count
DLC3
DLC2
DLC1
DLC0
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7
1000
8
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