參數(shù)資料
型號(hào): MC68HC05J1AVP
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: Microcontrollers
中文描述: 微控制器
文件頁數(shù): 38/128頁
文件大?。?/td> 1620K
代理商: MC68HC05J1AVP
Technical Data
MC68HC05J1A — Rev. 3.0
38
Central Processor Unit (CPU)
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Central Processor Unit (CPU)
3.3.5 Condition Code Register
The condition code register (CCR) shown in
Figure 3-6
is an 8-bit
register whose three most significant bits are permanently fixed at 111.
The condition code register contains the interrupt mask and four flags
that indicate the results of prior instructions.
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3
and 4 of the accumulator during an add without carry (ADD) or add
with carry (ADC) operation. The half-carry bit is required for
binary-coded decimal (BCD) arithmetic operations. Reset has no
effect on the half-carry flag.
I — Interrupt Mask Flag
Setting the interrupt mask (I) disables interrupts. If an interrupt
request occurs while the interrupt mask is a logic 0, the CPU saves
the CPU registers on the stack, sets the interrupt mask, and then
fetches the interrupt vector. If an interrupt request occurs while the
interrupt mask is set, the interrupt request is latched. The CPU
processes the latched interrupt as soon as the interrupt mask is
cleared again.
A return-from-interrupt (RTI) instruction pulls the CPU registers from
the stack, restoring the interrupt mask to its cleared state. After a
reset, the interrupt mask is set and can be cleared only by a clear
interrupt mask bit (CLI), STOP, or WAIT instruction.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
1
1
1
H
I
N
Z
C
Write:
Reset:
1
1
1
U
1
U
U
U
= Unimplemented
U = Unaffected
Figure 3-6. Condition Code Register (CCR)
F
Freescale Semiconductor, Inc.
n
.
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