MC68F375
CONFIGURABLE TIMER MODULE (CTM9)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
13-40
13.7 Time Base Bus System
The time base bus (TBB) system makes it possible to freely configure connections
between counter submodules and action submodules. However the PWMSM sub-
modules are independent of the time base bus system. The CTM9 configuration is
13.7.1 Clock Selection
The PWMSM contains an 8-bit prescaler that is clocked by the PCLK1 signal from the
CPSM (i.e. the MCU system clock divided by 2 or by 3). A 3-bit field (CLK[2:0]) in the
PWMSM status, interrupt and control register (PWMSIC) allows the software to select
which of the 8 prescaler outputs drives the PWMSM counter. The prescaler outputs
are the main MCU clock divided by: 2, 4, 8, 16, 32, 64, 128 and 512 (or 3, 6, 12, 24,
48, 96, 192 and 768, if the divide-by-3 option is used in the CPSM to generate PCLK1).
13.7.2 The PWMSM Counter (PWMC)
The 16-bit up-counter in the PWMSM provides the time base for the PWM output sig-
nal. The counter is held in the 0x0001 state on reset or when the PWMSM is disabled.
When the PWMSM is enabled, the counter begins counting at the rate defined by the
clock selection. Each time the counter matches the contents of the period register, the
counter is preset to 0x0001 and starts to count from that value. The counter can be
read at any time without affecting its value. Writing to the counter has no effect.
13.7.3 PWMSM Period Registers and Comparator
The period section of the PWMSM consists of two 16-bit period registers (PWMA1 and
PWMA2) and one 16-bit comparator. PWMA2 holds the current PWM period value and
PWMA1 holds the next PWM period value. The software establishes the next period
of the output PWM signal by writing a value into PWMA1. PWMA2 acts as a double
buffer of PWMA1, allowing the contents of PWMA1 to be changed at any time without
affecting the current period of the output signal; it cannot be accessed directly by the
software. PWMA1 can be read or written at any time. The new value in the PWMA1
register is transferred to PWMA2 on the next full cycle of the output or when a ‘1’ is
written to the LOAD bit in the PWMSIC register.
The comparator continuously compares the contents of the PWMA2 register with the
value in the PWMSM counter. When a match occurs, the state sequencer sets the out-
put flip-flop and resets the counter to 0x0001.
Period values 0x0000 and 0x0001 are special cases. When PWMA2 contains 0x0000,
an output period of 65536 PWM clock periods is generated.
When PWMA2 contains 0x0001, a period match occurs on every PWM clock period:
the counter never increments beyond 0x0001 and the output level never changes.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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