MC68F375
CDR MoneT FLASH FOR THE IMB3 (CMFI)
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
10-17
7—
Reserved
6:0
CLKPM
Clock period multiple select. The CLKPM[6:0] bits are write protected by the SES bit. Writes to
CMFICTL will not change CLKPM[6:0] if SES = 1. The third term of the timing control is the linear
clock multiplier, M. The clock period multiplier, CLKPM[6:0], defines a linear multiplier for the
program or erase pulse. The multiplier, M, is defined by the equation:
M = 1 + CLKPM[6:0]
This allows for the program/erase pulse to be from 1 to 128 times the pulse set by the system
clock period, SCLKR[2:0] and CLKPE[1:0].
CMFICTL2 — CMFI High Voltage Control Register 2
0xYF F80E
MSB
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
LSB
0
BLOCK
0
PEEM
B0EM
0
PE
SES
EHV
RESET:
0
Table 10-10 CMFICTL2 Bit Settings
Bit(s)
Name
Description
15:8
BLOCK
Block program and erase select. The BLOCK[7:0] bits are write protected by the SES bit. Writes
to CMFICTL will not change BLOCK[7:0] if SES = 1. BLOCK[7:0] selects the CMFI EEPROM
array blocks for program and erase operation. Up to eight blocks may be selected for program
or erase operation at once. The CMFI EEPROM configuration along with BLOCK[7:0] determine
the blocks that will be programmed simultaneously. The CMFI EEPROM array blocks that are
selected to be programmed by the program operation are the blocks where BLOCK[M] = 1. The
CMFI EEPROM configuration along with BLOCK[7:0] determine the blocks that will be erased
simultaneously. The CMFI EEPROM array blocks that are selected to be erased by the erase
operation are the blocks where BLOCK[M] = 1.
WARNING
The block bit must be set only for the blocks currently being programed. If the block bits are set
for blocks that are not being programmed, the contents of the other blocks could be disturbed.
0 = Array block M is not selected for program or erase.
1 = Array block M is selected for program or erase.
7:6
—
Reserved
5
PEEM
Program erase enable monitor. The CMFI will sample the EPEE signal (always enabled on the
MC68F375) when EHV is asserted and hold the EPEE state until EHV is negated. The EPEE sig-
nal has a digital filter that requires two consecutive samples to be equal before the output of the
filter will change.
0 = High voltage operations are not possible.
1 = High voltage operations are possible.
4B0EM
Block zero enable monitor. The CMFI will sample B0EM when EHV is asserted and hold the
B0EM state until EHV is negated. The optional EPEB0 pin has a digital filter similar to the EPEE
signal. If B0EM = 1 when EHV is asserted, high voltage operations to CMFI array block 0 such
as program or erase are enabled. While, if B0EM = 0 when EHV is asserted high voltage oper-
ations to CMFI array block 0 are disabled.
0 = High voltage operations in Array Block 0 are not possible.
1 = High voltage operations in Array Block 0 are possible.
3—
Reserved
Table 10-9 CMFICTL1 Bit Settings (Continued)
Bit(s)
Name
Description
F
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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