MC68F375
TIME PROCESSOR UNIT 3
MOTOROLA
REFERENCE MANUAL
Rev. 25 June 03
8-11
Table 8-6 TPUMCR Bit Settings
Bit(s)
Name
Description
15
STOP
Low-power stop mode enable. If the STOP bit in TPUMCR is set, the TPU3 shuts down its inter-
nal clocks, shutting down the internal microengine. TCR1 and TCR2 cease to increment and
retain the last value before the stop condition was entered. The TPU3 asserts the stop flag (STF)
in TPUMCR to indicate that it has stopped.
0 = Enable TPU3 clocks
1 = Disable TPU3 clocks
14:13
TCR1P
Timer count register 1 prescaler control. TCR1 is clocked from the output of a prescaler. The
prescaler divides its input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in
TPUMCR3 is set.
00 = Divide by 1
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8
12:11
TCR2P
Timer count register 2 prescaler control. TCR2 is clocked from the output of a prescaler. The
prescaler divides this input by 1, 2, 4, or 8. This is a write-once field unless the PWOD bit in
TPUMCR3 is set.
00 = Divide by 1
01 = Divide by 2
10 = Divide by 4
11 = Divide by 8
10
EMU
Emulation control. In emulation mode, the TPU3 executes microinstructions from DPTRAM
exclusively. Access to the DPTRAM via the IMB3 is blocked, and the DPTRAM is dedicated for
use by the TPU3. After reset, this bit can be written only once.
0 = TPU3 and DPTRAM operate normally
1 = TPU3 and DPTRAM operate in emulation mode
9T2CG
TCR2 clock/gate control
0 = TCR2 pin used as clock source for TCR2
1 = TCR2 pin used as gate of DIV8 clock for TCR2
8STF
Stop flag.
0 = TPU3 is operating normally
1 = TPU3 is stopped (STOP bit has been set)
7SUPV
Supervisor data space
0 = Assignable registers are accessible from user or supervisor privilege level
1 = Assignable registers are accessible from supervisor privilege level only
6
PSCK
Standard prescaler clock. Note that this bit has no effect if the extended prescaler is selected
(EPSCKE = 1).
0 = fSYS ÷ 32 is input to TCR1 prescaler, if standard prescaler is selected
1 = fSYS ÷ 4 is input to TCR1 prescaler, if standard prescaler is selected
5TPU3
TPU3 enable. The TPU3 enable bit provides compatibility with the TPU. If running TPU code on
the TPU3, the microcode size should not be greater than 2 Kbytes and the TPU3 enable bit
should be cleared to zero. The TPU3 enable bit is write-once after reset. The reset value is one,
meaning that the TPU3 will operate in TPU3 mode.
0 = TPU mode; zero is the TPU reset value
1 = TPU3 mode; one is the TPU3 reset value
NOTE: The programmer should not change this value unless necessary when developing cus-
tom TPU microcode.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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