參數(shù)資料
型號： MC68711E20VFNE2
廠商： Freescale Semiconductor
文件頁數(shù)： 98/138頁
文件大小： 0K
描述： IC MCU 8BIT 52-PLCC
標準包裝： 23
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設備： POR，WDT
輸入/輸出數(shù)： 38
程序存儲器容量： 20KB（20K x 8）
程序存儲器類型： OTP
EEPROM 大?。?/td> 512 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據轉換器： A/D 8x8b
振蕩器型： 內部
工作溫度： -40°C ~ 105°C
封裝/外殼： 52-LCC（J 形引線）
包裝： 管件
Input/Output (I/O) Ports
MC68HC711D3 Data Sheet, Rev. 2.1
62
Freescale Semiconductor
PORTA can be read any time. Inputs return the pin level, whereas outputs return the pin driver input level.
If written, PORTA stores the data in an internal latch. It drives the pins only if they are configured as
outputs. Writes to PORTA do not change the pin state when the pins are configured for timer output
compares.
Out of reset, port A bits 7 and 3–0 are general high-impedance inputs, while bits 6–4 are outputs, driving
low. On bidirectional lines PA7 and PA3, the timer forces the I/O state to be an output if the associated
output compare is enabled. In this case, the data direction bits DDRA7 and DDRA3 in PACTL will not be
changed or have any effect on those bits. When the output compare functions associated with these pins
are disabled, the DDR bits in PACTL govern the I/O state.
5.3 Port B
Port B is an 8-bit, general-purpose I/O port with a data register (PORTB) and a data direction register
(DDRB).
In the single-chip mode, port B pins are general-purpose I/O pins (PB7–PB0).
In the expanded-multiplexed mode, all of the port B pins act as the high-order address bits
(A15–A8) of the address bus.
5.3.1 Port B Data Register
PORTB can be read at any time. Inputs return the sensed levels at the pin, while outputs return the input
level of the port B pin drivers. If PORTB is written, the data is stored in an internal latch and can be driven
only if port B is configured for general-purpose outputs in single-chip or bootstrap mode.
Port B pins are general--purpose inputs out of reset in single-chip and bootstrap modes. These pins are
outputs (the high-order address bits) out of reset in expanded multiplexed and test modes.
5.3.2 Port B Data Direction Register
DDB7–DDB0 — Data Direction Bits for Port B
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured for input only
Address:
$0004
Bit 7
654321
Bit 0
Read:
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Write:
Reset:
00000000
Alt. Func.:
A15
A14
A13
A12
A11
A10
A9
A8
Figure 5-2. Port B Data Register (PORTB)
Address:
$0006
Bit 7
654321
Bit 0
Read:
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Write:
Reset:
00000000
Figure 5-3. Data Direction Register for Port B (DDRB)
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