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參數(shù)資料
| 型號： | MC68711E20VFNE2 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 3/138頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 8BIT 52-PLCC |
| 標準包裝： | 23 |
| 系列： | HC11 |
| 核心處理器： | HC11 |
| 芯體尺寸： | 8-位 |
| 速度： | 4MHz |
| 連通性： | SCI，SPI |
| 外圍設(shè)備： | POR，WDT |
| 輸入/輸出數(shù)： | 38 |
| 程序存儲器容量： | 20KB（20K x 8） |
| 程序存儲器類型： | OTP |
| EEPROM 大?。?/td> | 512 x 8 |
| RAM 容量： | 768 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x8b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 52-LCC（J 形引線） |
| 包裝： | 管件 |
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Programmable Timer
MC68HC711D3 Data Sheet, Rev. 2.1
100
Freescale Semiconductor
DDRA7 — Data Direction Control for Port A Bit 7
Refer to 8.7 Pulse Accumulator.
PAEN — Pulse Accumulator System Enable Bit
Refer to 8.7 Pulse Accumulator.
PAMOD — Pulse Accumulator Mode Bit
Refer to 8.7 Pulse Accumulator.
PEDGE — Pulse Accumulator Edge Control Bit
Refer to 8.7 Pulse Accumulator.
DDRA3 — Data Direction Register for Port A Bit 3
Refer to Chapter 5 Input/Output (I/O) Ports.
I4/O5 — Input Capture 4/Output Compare 5 Bit
Refer to 8.3 Input Capture.
RTR1 and RTR0 — RTI Interrupt Rate Select Bits
These two bits determine the rate at which the RTI system requests interrupts. The RTI system is
driven by an E divided by 213 rate clock that is compensated so it is independent of the timer prescaler.
These two control bits select an additional division factor. See Table 8-6.
8.6 Computer Operating Properly Watchdog Function
The clocking chain for the COP function, tapped off of the main timer divider chain, is only superficially
related to the main timer system. The CR1 and CR0 bits in the OPTION register and the NOCOP bit in
the CONFIG register determine the status of the COP function. Refer to Chapter 4 Resets, Interrupts, and
Low-Power Modes for a more detailed discussion of the COP function.
8.7 Pulse Accumulator
The MC68HC711D3 has an 8-bit counter that can be configured to operate either as a simple event
counter or for gated time accumulation, depending on the state of the PAMOD bit in the PACTL register.
Refer to the pulse accumulator block diagram, Figure 8-19.
In the event counting mode, the 8-bit counter is clocked to increasing values by an external pin. The
maximum clocking rate for the external event counting mode is the E clock divided by two. In gated time
accumulation mode, a free-running E-clock
÷ 64 signal drives the 8-bit counter, but only while the external
PAI pin is activated. Refer to Table 8-7. The pulse accumulator counter can be read or written at any time.
Pulse accumulator control bits are also located within two timer registers, TMSK2 and TFLG2, as
described here.
Table 8-6. Real-Time Interrupt Rates
RTR1
and RTR0
E = 1 MHz
E = 2 MHz
E = 3 MHz
E = X MHz
0 0
0 1
1 0
1 1
2.731 ms
5.461 ms
10.923 ms
21.845 ms
4.096 ms
8.192 ms
16.384 ms
32.768 ms
8.192 ms
16.384 ms
32.768 ms
65.536 ms
(E/213)
(E/214)
(E/215)
(E/216)
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