參數(shù)資料
型號： MC68711E20VFNE2
廠商： Freescale Semiconductor
文件頁數(shù)： 39/138頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 52-PLCC
標(biāo)準(zhǔn)包裝： 23
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 38
程序存儲器容量： 20KB（20K x 8）
程序存儲器類型： OTP
EEPROM 大?。?/td> 512 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 52-LCC（J 形引線）
包裝： 管件
MC68L11D0 Electrical Characteristics
MC68HC711D3 Data Sheet, Rev. 2.1
Freescale Semiconductor
133
B.2.3 Control Timing
B.2.4 Peripheral Port Timing
Characteristic(1)
1. VDD = 3.0 Vdc to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
Symbol
1.0 MHz
2.0 MHz
Unit
Min
Max
Min
Max
Frequency of operation
fO
dc
1.0
dc
2.0
MHz
E-clock period
tcyc
1000
—
500
—
ns
Crystal frequency
fXTAL
—
4.0
—
8.0
MHz
External oscillator frequency
4 fO
dc
4.0
dc
8.0
MHz
Processor control setup time
tPCSU = 1/4 tcyc + 50 ns
tPCSU
325
—
200
—
ns
Reset input pulse width(2)
To guarantee external reset vector
Minimum input time can be preempted by internal reset
2. Reset is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to Chapter 4
PWRSTL
8
1
—
8
1
—
tcyc
Interrupt pulse width, PWIRQ = tcyc + 20 ns
IRQ edge-sensitive mode
PWIRQ
1020
—
520
—
ns
Wait recovery startup time
tWRS
—4
—
4
tcyc
Timer pulse width PWTIM = tcyc + 20 ns
Input capture pulse accumulator input
PWTIM
1020
—
520
—
ns
Characteristic(1)
1. VDD = 3.0 Vd to 5.5 Vdc, VSS = 0 Vdc, TA = TL to TH. All timing is shown with respect to 20% VDD and 70% VDD, unless
otherwise noted.
Symbol
1.0 MHz
2.0 MHz
Unit
Min
Max
Min
Max
Frequency of operation (E-clock frequency)
fO
dc
1.0
dc
2.0
MHz
E-clock period
tcyc
1000
—
500
—
ns
Peripheral data setup time(2)
MCU read of ports A, B, C, and D
2. Port C and D timing is valid for active drive (CWOM and DWOM bits not set in PIOC and SPCR registers respectively).
tPDSU
100
—
100
—
ns
Peripheral data hold time(2)
MCU read of ports A, B, C, and D
tPDH
50
—
50
—
ns
Delay time, peripheral data write
MCU write to port A
MCU writes to ports B, C, and D
tPWD = 1/4 tcyc + 150 ns
tPWD
—
200
350
—
200
225
ns
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