參數(shù)資料
型號(hào)： MC68711E20MFNE3
廠商： Freescale Semiconductor
文件頁數(shù)： 82/138頁
文件大?。?/td> 0K
描述： IC MCU 8BIT 52-PLCC
標(biāo)準(zhǔn)包裝： 23
系列： HC11
核心處理器： HC11
芯體尺寸： 8-位
速度： 4MHz
連通性： SCI，SPI
外圍設(shè)備： POR，WDT
輸入/輸出數(shù)： 38
程序存儲(chǔ)器容量： 20KB（20K x 8）
程序存儲(chǔ)器類型： OTP
EEPROM 大?。?/td> 512 x 8
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x8b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 125°C
封裝/外殼： 52-LCC（J 形引線）
包裝： 管件
Resets, Interrupts, and Low-Power Modes
MC68HC711D3 Data Sheet, Rev. 2.1
48
Freescale Semiconductor
The sequence for resetting the watchdog timer is:
1.
Write $55 to the COP reset register (COPRST) to arm the COP timer clearing mechanism.
2.
Write $AA to the COPRST register to clear the COP timer
Both writes must occur in this sequence prior to the timeout, but any number of instructions can be
executed between the two writes.
4.2.4 Clock Monitor Reset
The MCU contains a clock monitor circuit that measures the E-clock frequency. If the E-clock input rate
is above approximately 200 kHz, then the clock monitor does not generate an MCU reset. If the E-clock
signal is lost or its frequency falls below 10 kHz, then an MCU reset can be generated, and the RESET
pin is driven low to reset the external system.
4.2.5 System Configuration Options Register
The system configuration options register (OPTION) is a special-purpose register with several
time-protected bits. OPTION is used during initialization to configure internal system options.
Bits 5, 4, 2, 1, and 0 can be written only once during the first 64 E-clock cycles after reset in normal modes
(where the HPRIO register bit (SMOD) is cleared). In special modes (where SMOD = 1), the bits can be
written at any time. Bit 3 can be written at anytime.
Table 4-1. COP Time Out Periods
CR0 CR1
E
÷ 215
Divided
By
XTAL = 223
Time Out
–0/+15.6 ms
XTAL =
8.0 MHz
Time Out
–0/+16.4 ms
XTAL =
4.9152 MHz
Time Out
–0/+26.7 ms
XTAL =
4.0 MHz
Time Out
–0/+32.8 ms
XTAL =
3.6864 MHz
Time Out
–0/+35.6 ms
0
1
15.625 ms
16.384 ms
26.667 ms
32.768 ms
35.556 ms
0
1
4
62.5 ms
65.536 ms
106.67 ms
131.07 ms
142.22 ms
1
0
16
250 ms
262.14 ms
426.67 ms
524.29 ms
568.89 ms
1
64
1 sec
1.049 sec
1.707 sec
2.1 sec
2.276 ms
E =
2.1 MHz
2.0 MHz
1.2288 MHz
1.0 MHz
921.6 kHz
Address:
$003A
Bit 7
654321
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
00000000
Figure 4-1. Arm/Reset COP Timer Circuitry Register (COPRST)
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