參數(shù)資料
型號: MC68711E20MFNE3
廠商: Freescale Semiconductor
文件頁數(shù): 129/138頁
文件大?。?/td> 0K
描述: IC MCU 8BIT 52-PLCC
標(biāo)準(zhǔn)包裝: 23
系列: HC11
核心處理器: HC11
芯體尺寸: 8-位
速度: 4MHz
連通性: SCI,SPI
外圍設(shè)備: POR,WDT
輸入/輸出數(shù): 38
程序存儲器容量: 20KB(20K x 8)
程序存儲器類型: OTP
EEPROM 大?。?/td> 512 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 52-LCC(J 形引線)
包裝: 管件
Programmable Timer
MC68HC711D3 Data Sheet, Rev. 2.1
90
Freescale Semiconductor
8.3.3 Timer Input Capture 4/Output Compare 5 Register
Use timer input capture 4/output compare 5 (TI4/O5) as either an input capture register or an output
compare register, depending on the function chosen for the I4/O5 pin. To enable it as an input capture
pin, set the I4/O5 bit in the pulse accumulator control register (PACTL) to logic level 1. To use it as an
output compare register, set the I4/O5 bit to a logic level 0. Refer to 8.7 Pulse Accumulator.
Address: $0011 — TIC1 (Low)
Bit 7
654321
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Address: $0012 — TIC2 (High)
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Unaffected by reset
Address: $0013 — TIC2 (Low)
Bit 7
654321
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Address: $0014 — TIC3 (High)
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
Unaffected by reset
Address: $0015 — TIC3 (Low)
Bit 7
654321
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Unaffected by reset
Address: $001E — TI4/O5 (High)
Bit 15
14
13
12
11
10
9
Bit 8
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset:
11111111
Address: $001F — TI4/O5 (Low)
Bit 7
654321
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
11111111
= Unimplemented
Figure 8-5. Timer Input Capture 4/Output
Compare 5 Register (TI4/O5)
= Unimplemented
Figure 8-4. Timer Input Capture Registers (TICx) (Continued)
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