參數(shù)資料
型號: MC56F8355MFGE
廠商: Freescale Semiconductor
文件頁數(shù): 88/172頁
文件大小: 0K
描述: IC DSP 16BIT 60MHZ 128-LQFP
標(biāo)準(zhǔn)包裝: 72
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 264KB(132K x 16)
程序存儲器類型: 閃存
RAM 容量: 10K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 128-LQFP
包裝: 托盤
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8355 Technical Data, Rev. 17
22
Freescale Semiconductor
Preliminary
GPIOB4
(A20)
(prescaler_
clock)
31
Schmitt
Input/
Output
Input,
pullup
enabled
Port B GPIO — This GPIO pin can be individually programmed as
an input or output pin.
Address Bus — A20 specifies one of the address lines for
external program or data memory accesses. Depending upon the
state of the DRV bit in the EMI bus control register (BCR), A20
and EMI control signals are tri-stated when the external bus is
inactive.
Clock Output — can be used to monitor the prescaler_clock on
GPIOB4.
After reset, the default state is GPIO.
This pin can also be used to view the prescaler_clock. In these
cases, the GPIOB_PER can be used to disable the GPIO. The
CLKOSR register in the SIM can then be used to choose between
address and clock functions; see Part 6.5.7 for details.
To deactivate the internal pullup resistor, clear clear bit 4 in the
GPIOB_PUR register.
D7
(GPIOF0)
22
Input/
Output
Input/
Output
In reset,
output is
disabled,
pullup is
enabled
Data Bus — D7 - D10 specify part of the data for external
program or data memory accesses. Depending upon the state of
the DRV bit in the EMI bus control register (BCR), D7 - D10 are
tri-stated when the external bus is inactive
Port F GPIO — These four GPIO pins can be individually
programmed as input or output pins.
After reset, these pins default to data bus functionality and should
be programmed as GPIO.
To deactivate the internal pullup resistor, clear the appropriate
GPIO bit in the GPIOF_PUR register.
Example: GPIOF0, clear bit 0 in the GPIOF_PUR register.
Note: Primary function is not available in this package
configuration; GPIO function must be used instead.
D8
(GPIOF1)
23
D9
(GPIOF2)
24
D10
(GPIOF3)
26
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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