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參數(shù)資料
型號: MC56F8355MFGE
廠商: Freescale Semiconductor
文件頁數(shù): 86/172頁
文件大小: 0K
描述: IC DSP 16BIT 60MHZ 128-LQFP
標準包裝: 72
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 49
程序存儲器容量: 264KB(132K x 16)
程序存儲器類型: 閃存
RAM 容量: 10K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 128-LQFP
包裝: 托盤
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
56F8355 Technical Data, Rev. 17
20
Freescale Semiconductor
Preliminary
VSSA_ADC
95
Supply
ADC Analog Ground — This pin supplies an analog ground to
the ADC modules.
OCR_DIS
71
Input
On-Chip Regulator Disable
Tie this pin to VSS to enable the on-chip regulator.
Tie this pin to VDD to disable the on-chip regulator.
This pin is intended to be a static DC signal from power-up to
shut down. Do no try to toggle this pin for power savings
during operation.
VCAP1
49
Supply
VCAP1 - 4 — When OCR_DIS is tied to VSS (regulator enabled),
connect each pin to a 2.2
μF or greater bypass capacitor in order
to bypass the core logic voltage regulator, required for proper chip
operation. When OCR_DIS is tied to VDD (regulator disabled),
these pins become VDD_CORE and should be connected to a
regulated 2.5V power supply.
Note: This bypass is required even if the chip is powered with
an external supply.
VCAP2
122
VCAP3
75
VCAP4
13
VPP1
119
Input
VPP1 - VPP2 — These pins should be left unconnected as an open
circuit for normal functionality.
VPP2
5
CLKMODE
79
Input
Clock Input Mode Selection — This input determines the
function of the XTAL and EXTAL pins.
1 = External clock input on XTAL is used to directly drive the input
clock of the chip. The EXTAL pin should be grounded.
0 = A crystal or ceramic resonator should be connected between
XTAL and EXTAL.
EXTAL
74
Input
External Crystal Oscillator Input — This input can be connected
to an 8MHz external crystal. Tie this pin low if XTAL is driven by
an external clock source.
XTAL
73
Input/
Output
Chip-driven
Crystal Oscillator Output — This output connects the internal
crystal oscillator output to an external crystal.
If an external clock is used, XTAL must be used as the input and
EXTAL connected to GND.
The input clock can be selected to provide the clock directly to the
core. This input clock can also be selected as the input clock for
the on-chip PLL.
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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