參數(shù)資料
型號: MC56F8347MPY60
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: LQFP-160
文件頁數(shù): 74/160頁
文件大小: 2217K
代理商: MC56F8347MPY60
20
56F8347 Technical Data
Preliminary
WR
51
Output
Tri-stated
Write Enable — WR is asserted during external memory
write cycles. When WR is asserted low, pins D0 - D15
become outputs and the device puts data on the bus.
When WR is deasserted high, the external data is latched
inside the external device. When WR is asserted, it
qualifies the A0 - A16, PS, and DS pins. WR can be
connected directly to the WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A0 - A23 and EMI control signals
are tri-stated when the external bus is inactive.
To deactivate the internal pull-up resistor, set the CTRL bit
in the SIM_PUDR register.
PS
(CS0)
(GPIOD8)
53
Output
Input/
Output
Tri-stated
Program Memory Select — This signal is actually CS0 in
the EMI, which is programmed at reset for compatibility
with the 56F80x PS signal. PS is asserted low for external
program memory access.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A0 - A23 and EMI control signals
are tri-stated when the external bus is inactive.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
CS0 resets to provide the PS function as defined on the
56F80x devices.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
DS
(CS1)
(GPIOD9)
54
Output
Input/
Output
Tri-stated
Data Memory Select — This signal is actually CS1 in the
EMI, which is programmed at reset for compatibility with
the 56F80x DS signal. DS is asserted low for external data
memory access.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A0 - A23 and EMI control signals
are tri-stated when the external bus is inactive.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
Table 2-2 56F8347 Signal and Package Information for the 160-Pin LQFP
Signal Name
Pin No.
Type
State
During
Reset
Signal Description
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